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參數(shù)資料
| 型號(hào)： | 935230900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 52/68頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | 935230900112 |
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2000 Jan 04
56
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
6.5.4.1
CD.2 to CD.0
The bits CD.2 to CD.0 are accessible without restrictions in reset mode as well as in operating mode. These bits are used
to define the frequency at the external CLKOUT pin. For an overview of selectable frequencies see Table 50.
Table 50 CLKOUT frequency selection; note 1
Note
1. fosc is the frequency of the external oscillator (XTAL).
CD.2
CD.1
CD.0
CLKOUT FREQUENCY
000
001
010
011
100
101
110
111
fosc
f
osc
2
--------
f
osc
4
--------
f
osc
6
--------
f
osc
8
--------
f
osc
10
--------
f
osc
12
--------
f
osc
14
--------
6.5.4.2
Clock off
Setting this bit allows the external CLKOUT pin of the
SJA1000 to be disabled. A write access is possible only in
reset mode. If this bit is set, CLKOUT is LOW during sleep
mode, otherwise it is HIGH.
6.5.4.3
RXINTEN
This bit allows the TX1 output to be used as a dedicated
receive interrupt output. When a received message has
passed the acceptance filter successfully, a receive
interrupt pulse with the length of one bit time is always
output at the TX1 pin (during the last bit of end of frame).
The transmit output stage should operate in normal output
mode. The polarity and output drive are programmable via
the output control register (see also Section 6.5.3). A write
access is only possible in reset mode.
6.5.4.4
CBP
Setting of CDR.6 allows to bypass the CAN input
comparator and is only possible in reset mode. This is
useful in the event that the SJA1000 is connected to an
external transceiver circuit. The internal delay of the
SJA1000 is reduced, which will result in a longer maximum
possible bus length. If CBP is set, only RX0 is active. The
unused RX1 input should be connected to a defined level
(e.g. VSS).
6.5.4.5
CAN mode
CDR.7 defines the CAN mode. If CDR.7 is at logic 0 the
CAN controller operates in BasicCAN mode. If set to
logic 1 the CAN controller operates in PeliCAN mode.
Write access is only possible in reset mode.
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