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參數(shù)資料
| 型號(hào)： | 935230900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 4/68頁 |
| 文件大小： | 234K |
| 代理商： | 935230900112 |
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2000 Jan 04
12
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Notes
1. X means that the value of these registers or bits is not influenced.
2. Remarks in brackets explain functional meaning.
3. Reading the command register will always reflect a binary ‘11111111’.
4. On bus-off the error interrupt is set, if enabled.
5. Internal read/write pointers of the RXFIFO are reset to their initial values. A subsequent read access to the RXB
would show undefined data values (parts of old messages). If a message is transmitted, this message is written in
parallel to the receive buffer but no receive interrupt is generated and the receive buffer area is not locked. So, even
if the receive buffer is empty, the last transmitted message may be read from the receive buffer until it is overridden
by the next received or transmitted message.
Upon a hardware reset, the RXFIFO pointers are reset to the physical RAM address ‘0’. Setting CR.0 by software or
due to the bus-off event will reset the RXFIFO pointers to the currently valid FIFO start address which is different
from the RAM address ‘0’ after the first release receive buffer command.
6.3.3
CONTROL REGISTER (CR)
The contents of the control register are used to change the behaviour of the CAN controller. Bits may be set or reset by
the attached microcontroller which uses the control register as a read/write memory.
Table 3
Bit interpretation of the control register (CR); CAN address 0
BIT
SYMBOL
NAME
VALUE
FUNCTION
CR.7
reserved; note 1
CR.6
reserved; note 2
CR.5
reserved; note 3
CR.4
OIE
Overrun Interrupt Enable
1
enabled; if the data overrun bit is set, the
microcontroller receives an overrun interrupt
signal (see also status register; Table 5)
0
disabled; the microcontroller receives no overrun
interrupt signal from the SJA1000
CR.3
EIE
Error Interrupt Enable
1
enabled; if the error or bus status change, the
microcontroller receives an error interrupt signal
(see also status register; Table 5)
0
disabled; the microcontroller receives no error
interrupt signal from the SJA1000
CR.2
TIE
Transmit Interrupt Enable
1
enabled; when a message has been successfully
transmitted or the transmit buffer is accessible
again, (e.g. after an abort transmission command)
the SJA1000 transmits a transmit interrupt signal
to the microcontroller
0
disabled; the microcontroller receives no transmit
interrupt signal from the SJA1000
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