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| 型號(hào)： | 935230900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 51/68頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | 935230900112 |
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2000 Jan 04
55
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Table 48 Output pin conguration; note 1
Notes
1. X = don’t care.
2. TPX is the on-chip output transistor X, connected to VDD.
3. TNX is the on-chip output transistor X, connected to VSS.
4. TXX is the serial output level on pin TX0 or TX1. It is required that the output level on the CAN-bus line is dominant
when TXD = 0 and recessive when TXD = 1.
DRIVE
TXD
OCTPX
OCTNX
OCPOLX
TPX(2)
TNX(3)
TXX(4)
Float
X
0
X
off
oat
Pull-down
0
1
0
off
on
LOW
1
0
1
0
off
oat
0
1
off
oat
1
0
1
off
on
LOW
Pull-up
0
1
0
off
oat
1
0
on
off
HIGH
0
1
0
1
on
off
HIGH
1
0
1
off
oat
Push-pull
0
1
0
off
on
LOW
1
0
on
off
HIGH
0
1
on
off
HIGH
1
off
on
LOW
The bit sequence (TXD) is sent via TX0 and TX1.
The voltage levels on the output driver pins depends on
both the driver characteristics programmed by OCTP,
OCTN (float, pull-up, pull-down, push-pull) and the output
polarity programmed by OCPOL.
6.5.4
CLOCK DIVIDER REGISTER (CDR)
The clock divider register controls the CLKOUT frequency
for the microcontroller and allows to deactivate the
CLKOUT pin. Additionally a dedicated receive interrupt
pulse on TX1, a receive comparator bypass and the
selection between BasicCAN mode and PeliCAN mode is
made here. The default state of the register after hardware
reset is divide-by-12 for Motorola mode (00000101) and
divide-by-2 for Intel mode (00000000).
On software reset (reset request/reset mode) this register
is not influenced.
The reserved bit (CDR.4) will always reflect a logic 0.
The application software should always write a logic 0 to
this bit in order to be compatible with future features, which
may be 1-active using this bit.
Table 49 Bit interpretation of the clock divider register (CDR); CAN address 31
Note
1. This bit cannot be written. During read-out of this register always a zero is given.
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
CAN mode
CBP
RXINTEN
(0)(1)
clock off
CD.2
CD.1
CD.0
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