
Intel
82801BA ICH2 Datasheet
9-41
LPC Interface Bridge Registers (D31:F0)
9.5
Advanced Interrupt Controller (APIC)
9.5.1
APIC Register Map
The APIC is accessed via an indirect addressing scheme. Two registers are visible by software for
manipulation of most of the APIC registers. These registers are mapped into memory space. The
registers are shown in
Table 9-4
.
Table 9-5
lists the registers which can be accessed within the APIC via the Index Register. When
accessing these registers, accesses must be done a DWord at a time. For example, software should
never access byte 2 from the Data register before accessing bytes 0 and 1. The hardware will not
attempt to recover from a bad programming model in this case.
9.5.2
IND—Index Register
Memory Address
Default Value:
FEC0_0000h
00h
Attribute:
Size:
R/W
8 bits
The Index Register will select which APIC indirect register to be manipulated by software. The
selector values for the indirect registers are listed in
Table 9-5
. Software programs this register to
select the desired APIC internal register
.
Table 9-4. APIC Direct Registers
Address
Register
Size
Type
FEC0_0000h
Index Register
8 bits
R/W
FEC0_0010h
Data Register
32 bits
R/W
FECO_0020h
IRQ Pin Assertion Register
8 bits
WO
FECO_0040h
EOI Register
8 bits
WO
Table 9-5. APIC Indirect Registers
Index
Register
Size
Type
00h
ID
32 bits
R/W
01h
Version
32 bits
RO
02h
Arbitration ID
32 bits
RO
03h
Boot Configuration
32 bits
R/W
03h–0Fh
Reserved
RO
10h –11h
Redirection Table 0
64 bits
R/W
12h–13h
Redirection Table 1
64 bits
R/W
...
...
...
...
3Eh–3Fh
Redirection Table 23
64 bits
R/W
40h–FFh
Reserved
RO
Bit
Description
7:0
APIC Index
—R/W.
This is an 8 bit pointer into the I/O APIC register table.
Powered by ICminer.com Electronic-Library Service CopyRight 2003