
Intel
82801BA ICH2 Datasheet
8-1
Hub Interface to PCI Bridge Registers (D30:F0)
Hub Interface to PCI Bridge Registers
(D30:F0)
8
The hub interface to PCI Bridge resides in PCI Device 30, Function 0 on bus #0. This portion of the
ICH2 implements the buffering and control logic between PCI and the hub interface. The
arbitration for the PCI bus is handled by this PCI device. The PCI decoder in this device must
decode the ranges for the hub interface. All register contents will be lost when core well power is
removed.
8.1
PCI Configuration Registers (D30:F0)
Note:
Registers that are not shown should be treated as Reserved (See
Section 6.2
for details).
.
Table 8-1. PCI Configuration Map (HUB-PCI—D30:F0)
Offset
Mnemonic
Register Name/Function
Default
Type
00–01h
VID
Vendor ID
8086h
RO
02–03h
DID
Device ID
244Eh
RO
04–05h
CMD
PCI Device Command Register
0001h
R/W
06–07h
PD_STS
PCI Device Status Register
0080h
R/W
08h
REVID
Revision ID
See Note
RO
0Ah
SCC
Sub Class Code
04h
RO
0Bh
BCC
Base Class Code
06h
RO
0Dh
PMLT
Primary Master Latency Timer
00h
RO
0Eh
HEADTYP
Header Type
01h
RO
18h
PBUS_NUM
Primary Bus Number
00h
RO
19h
SBUS_NUM
Secondary Bus Number
00h
R/W
1Ah
SUB_BUS_NUM
Subordinate Bus Number
00h
R/W
1Bh
SMLT
Secondary Master Latency Timer
00h
R/W
1Ch
IOBASE
IO Base Register
F0h
R/W
1Dh
IOLIM
IO Limit Register
00h
R/W
1E–1Fh
SECSTS
Secondary Status Register
0280h
R/W
20–21h
MEMBASE
Memory Base
FFF0h
R/W
22–23h
MEMLIM
Memory Limit
0000h
R/W
24–25h
PREF_MEM_BASE
Prefetchable Memory Base
0000h
RO
26–27h
PREF_MEM_MLT
Prefetchable Memory Limit
0000h
RO
30–31h
IOBASE_HI
I/O Base Upper 16 Bits
0000h
RO
32–33h
IOLIMIT_HI
I/O Limit Upper 16 Bits
0000h
RO
3Ch
INT_LINE
Interrupt Line
00h
RO
3E–3Fh
BRIDGE_CNT
Bridge Control
0000h
R/W
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