
LPC Interface Bridge Registers (D31:F0)
9-6
Intel
82801BA ICH2 Datasheet
9.1.10
PMBASE—ACPI Base Address (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
40–43h
00000001h
No
Attribute:
Size:
Usage:
Power Well:
R/W
32-bit
ACPI, Legacy
Core
Sets base address for ACPI I/O registers, GPIO registers and TCO I/O registers. Can be mapped
anywhere in the 64 KB I/O space on 128-byte boundaries.
9.1.11
ACPI_CNTL—ACPI Control (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
44h
00h
No
Attribute:
Size:
Usage:
Power Well:
R/W
8-bit
ACPI, Legacy
Core
Bit
Description
31:16
Reserved.
15:7
Base Address
—R/W. Provides 128 bytes of I/O space for ACPI, GPIO, and TCO logic. This is
placed on a 128-byte boundary.
6:1
Reserved.
0
Resource Indicator
—RO. Tied to 1 to indicate I/O space.
Bit
Description
7:5
Reserved.
4
ACPI Enable (ACPI_EN)
—R/W.
1 = Decode of the I/O range pointed to by the ACPI base register is enabled, and the ACPI power
management function is enabled. Note that the APM power management ranges (B2/B3h) are
always enabled and are not affected by this bit.
0 = Disable.
3
Reserved.
2:0
SCI IRQ Select (SCI_IRQ_SEL)
—R/W. Specifies on which IRQ the SCI will internally appear. If not
using the APIC, the SCI must be routed to IRQ[9:11], and that interrupt is not sharable with the
SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the SCI can also be
mapped to IRQ[20:23], and can be shared with other interrupts.
000 = IRQ9
001 = IRQ10
010 = IRQ11
011 = Reserved
100 = IRQ20 (Only available if APIC enabled)
101 = IRQ21 (Only available if APIC enabled)
110 = RQ22 (Only available if APIC enabled)
111 = IRQ23 (Only available if APIC enabled)
Powered by ICminer.com Electronic-Library Service CopyRight 2003