參數(shù)資料
型號： 6PAIC3106IRGZRQ1
廠商： Texas Instruments
文件頁數(shù)： 84/103頁
文件大小： 0K
描述： IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝： 1
類型： 立體聲音頻
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 102（差分），92 / 95（單端）
動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 91 / 99（差分），91 / 92（單端）
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-VQFN 裸露焊盤（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1077 (CN2011-ZH PDF)
其它名稱： 296-25253-6
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Table 108. Page 0 / Register 99: GPIO2 Control Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D4
R/W
0000
GPIO2 Output Control
0000: GPIO2 is disabled
0001: Reserved. Do not use.
0010: GPIO2 output = jack/headset detect interrupt (interrupt polarity: active high. Typical interrupt
duration: 1.75 ms.)
0011: GPIO2 = general purpose input
0100: GPIO2 = general purpose output
0101–0111: GPIO2 input = digital microphone input, data sampled on clock rising and falling edges
1000: GPIO2 = bit clock for audio serial data bus (programmable as input or output)
1001: GPIO2 output = Headset detect OR button press interrupt
1010: GPIO2 output = Headset detect OR button press OR short-circuit detect OR AGC noise detect
interrupt
1011: GPIO2 output = Short-circuit detect OR AGC noise detect interrupt
1100: GPIO2 output = Headset detect OR button press OR short-circuit detect interrupt
1101: GPIO2 output = Short-circuit detect interrupt
1110: GPIO2 output = AGC noise detect interrupt
1111: GPIO2 output = Button press / hookswitch interrupt
D3
R/W
0
GPIO2 General Purpose Output Value
0: GPIO1 outputs a logic-low level
1: GPIO1 outputs a logic-high level
D2
R
0
GPIO2 General Purpose Input Value
0: A logic-low level is input to GPIO2
1: A logic-high level is input to GPIO2
D1
R/W
0
GPIO2 Interrupt Duration Control
0: GPIO2 Interrupt occurs as a single active-high pulse of typical duration 2ms.
1: GPIO2 Interrupt occurs as continuous pulses until the Interrupt Flags register (register 96) is read by
the host
D0
R
0
Reserved. Don’t write to this register bit.
Table 109. Page 0 / Register 100: Additional GPIO Control Register A
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D6
R/W
00
SDA Pin Control (1)
The SDA pin hardware includes pulldown capability only (open-drain NMOS), so an external pullup
resistor is required when using this pin, even in GPIO mode.
00: SDA pin is not used as general purpose I/O
01: SDA pin used as general purpose input
10: SDA pin used as general purpose output
11: Reserved. Do not write this sequence to these register bits.
D5
R/W
0
SDA General Purpose Output Control (1)
0: SDA driven to logic-low when used as general-purpose output
1: SDA driven to logic-high when used as general-purpose output (requires external pullup resistor)
D4
R
0
SDA General Purpose Input Value (1)
0: SDA detects a logic-low when used as general-purpose input
1: SDA is detects a logic-high when used as general purpose input
D3–D2
R/W
00
SCL Pin Control(1)
The SCL pin hardware includes pulldown capability only (open-drain NMOS), so an external pullup
resistor is required when using this pin, even in GPIO mode.
00: SCL pin is not used as general purpose I/O
01: SCL pin used as general purpose input
10: SCL pin used as general purpose output
11: Reserved. Do not write this sequence to these register bits.
D1
R/W
0
SCL General Purpose Output Control (1)
0: SCL driven to logic-low when used as general-purpose output
1: SCL driven to logic-high when used as general-purpose output (requires external pullup resistor)
D0
R
0
SCL General Purpose Input Value (1)
0: SCL detects a logic-low when used as general-purpose input
1: SCL detects a logic-high when used as general-purpose input
(1)
The control bits in Register 100 are only valid in SPI Mode, when SELECT=1.
Copyright 2009–2012, Texas Instruments Incorporated
81
Product Folder Links: TLV320AIC3106-Q1
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