參數(shù)資料
型號(hào): 6PAIC3106IRGZRQ1
廠商: Texas Instruments
文件頁數(shù): 43/103頁
文件大?。?/td> 0K
描述: IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 立體聲音頻
數(shù)據(jù)接口: 串行
分辨率(位): 24 b
ADC / DAC 數(shù)量: 2 / 2
三角積分調(diào)變:
S/N 比,標(biāo)準(zhǔn) ADC / DAC (db): 92 / 102(差分),92 / 95(單端)
動(dòng)態(tài)范圍,標(biāo)準(zhǔn) ADC / DAC (db): 91 / 99(差分),91 / 92(單端)
電壓 - 電源,模擬: 2.7 V ~ 3.6 V
電壓 - 電源,數(shù)字: 1.1 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-VQFN 裸露焊盤(7x7)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 1077 (CN2011-ZH PDF)
其它名稱: 296-25253-6
VOLUME
CONTROLS,
MIXING
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
DAC_L3
LEFT_LOP
LEFT_LOM
Gain = 0dB to +9dB,
Mute
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
DAC_R3
RIGHT_LOP
RIGHT_LOM
Gain = 0dB to +9 dB,
Mute
LINE2L
LINE2R
PGA_L
PGA_R
DAC_L1
DAC_R1
MONO_LOP
MONO_LOM
Gain = 0dB to +9dB,
Mute
DAC_L
DAC_L1
DAC_L2
DAC_L3
DAC_R
DAC_R1
DAC_R2
DAC_R3
STEREO
AUDIO
DAC
VOLUME
CONTROLS,
MIXING
VOLUME
CONTROLS,
MIXING
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
ANALOG FULLY DIFFERENTIAL LINE OUTPUT DRIVERS
The TLV320AIC3106 has two fully differential line output drivers, each capable of driving a 10-k
differential
load. The output stage design leading to the fully differential line output drivers is shown in Figure 34 and
Figure 35. This design includes extensive capability to adjust signal levels independently before any mixing
occurs, beyond that already provided by the PGA gain and the DAC digital volume control.
The LINE2L/R signals refer to the signals that travel through the analog input bypass path to the output stage.
The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC to
the output stage. Note that since both left and right channel signals are routed to all output drivers, a mono mix
of any of the stereo signals can easily be obtained by setting the volume controls of both left and right channel
signals to –6 dB and mixing them. Undesired signals can also be disconnected from the mix as well through
register control.
Figure 34. Architecture of the Output Stage Leading to the Fully Differential Line Output Drivers
44
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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