參數(shù)資料
型號(hào)： 6PAIC3106IRGZRQ1
廠商： Texas Instruments
文件頁數(shù)： 53/103頁
文件大?。?/td> 0K
描述： IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝： 1
類型： 立體聲音頻
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 102（差分），92 / 95（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 91 / 99（差分），91 / 92（單端）
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-VQFN 裸露焊盤（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1077 (CN2011-ZH PDF)
其它名稱： 296-25253-6
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Table 18. Page 0 / Register 10: Audio Serial Data Interface Control Register C
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7–D0
R/W
0000 0000
Audio Serial Data Word Offset Control
This register determines where valid data is placed or expected in each frame, by controlling the offset
from beginning of the frame where valid data begins. The offset is measured from the rising edge of word
clock when in DSP mode.
0000 0000: Data offset = 0 bit clocks
0000 0001: Data offset = 1 bit clock
0000 0010: Data offset = 2 bit clocks
…
Note: In continuous transfer mode the maximum offset is 17 for I2S/LJF/RJF modes and 16 for DSP
mode. In 256-clock mode, the maximum offset is 242 for I2S/LJF/RJF and 241 for DSP modes.
1111 1110: Data offset = 254 bit clocks
1111 1111: Data offset = 255 bit clocks
Table 19. Page 0 / Register 11: Audio Codec Overflow Flag Register
READ/
RESET
BIT
DESCRIPTION
WRITE
VALUE
D7
R
0
Left ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. The
register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D6
R
0
Right ADC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. The
register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D5
R
0
Left DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. The
register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D4
R
0
Right DAC Overflow Flag
This is a sticky bit, so will stay set if an overflow occurs, even if the overflow condition is removed. The
register bit reset to 0 after it is read.
0: No overflow has occurred
1: An overflow has occurred
D3–D0
R/W
0001
PLL R Value
0000: R = 16
0001 : R = 1
0010 : R = 2
0011 : R = 3
0100 : R = 4
…
1110: R = 14
1111: R = 15
Copyright 2009–2012, Texas Instruments Incorporated
53
Product Folder Links: TLV320AIC3106-Q1
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