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參數(shù)資料
| 型號： | 6PAIC3106IRGZRQ1 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 31/103頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CODEC STEREO 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 102（差分），92 / 95（單端） |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 91 / 99（差分），91 / 92（單端） |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-VQFN 裸露焊盤（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1077 (CN2011-ZH PDF) |
| 其它名稱： | 296-25253-6 |
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AudioSerialBusInterface
PGA
0/+59.5dB
0.5dBsteps
ADC
+
DAC
L
Volume
Control
DIN
DOUT
BCLK
WCLK
DINL
DINR
DOUTL
DOUTR
ADC
PGA
0/+59.5dB
0.5dBsteps
+
DACR
Volume
Control
Effects
AGC
RecordPath
DAC
Powered
Down
DAC
Powered
Down
Effects
SW-D1
SW-D2
SW-D3
SW-D4
LeftChannel
AnalogInputs
RightChannel
AnalogInputs
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Figure 27. Record Only Mode With Digital Processing Path Enabled
AUTOMATIC GAIN CONTROL (AGC)
An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant
output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry
automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a
person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several
programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum
PGA gain applicable that allow the algorithm to be fine tuned for any particular application. The algorithm uses
the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the
nominal amplitude of the output signal.
Note that completely independent AGC circuitry is included with each ADC channel with entirely independent
control over the algorithm from one channel to the next. This is attractive in cases where two microphones are
used in a system, but may have different placement in the end equipment and require different dynamic
performance for optimal system operation.
Target level represents the nominal output level at which the AGC attempts to hold the ADC output signal level.
The TLV320AIC3106 allows programming of eight different target levels, which can be programmed from –5.5
dB to –24 dB relative to a full-scale signal. Since the device reacts to the signal absolute average and not to
peak levels, it is recommended that the target level be set with enough margin to avoid clipping at the occurrence
of loud sounds.
Attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It
can be varied from 7 ms to 1,408 ms. The extended Right Channel Attack time can be programmed by writing to
Page 0, Registers 103, and Left Channel is programmed by writing to Page 0, Register 105.
Copyright 2009–2012, Texas Instruments Incorporated
33
Product Folder Links: TLV320AIC3106-Q1
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