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| 型號： | 6PAIC3106IRGZRQ1 |
| 廠商： | Texas Instruments |
| 文件頁數(shù)： | 41/103頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CODEC STEREO 48-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 立體聲音頻 |
| 數(shù)據(jù)接口： | 串行 |
| 分辨率（位）： | 24 b |
| ADC / DAC 數(shù)量： | 2 / 2 |
| 三角積分調(diào)變： | 是 |
| S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： | 92 / 102（差分），92 / 95（單端） |
| 動態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： | 91 / 99（差分），91 / 92（單端） |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 1.1 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-VQFN 裸露焊盤（7x7） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 1077 (CN2011-ZH PDF) |
| 其它名稱： | 296-25253-6 |
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SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
ADC PGA SIGNAL BYPASS PATH FUNCTIONALITY
In addition to the input bypass path described above, the TLV320AIC3106 also includes the ability to route the
ADC PGA output signals past the ADC, for mixing with other analog signals and then direct connection to the
output drivers. These bypass functions are described in more detail in the sections on output mixing and output
driver configurations.
INPUT IMPEDANCE AND VCM CONTROL
The TLV320AIC3106 includes several programmable settings to control analog input pins, particularly when they
are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a 3-
state condition, such that the input impedance seen looking into the device is extremely high. Note, however, that
the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any voltage is
driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS, these
protection diodes will begin conducting current, resulting in an effective impedance that no longer appears as a
3-state condition.
Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input
voltage of the ADC PGA (which is determined by an internal bandgap voltage reference). This is useful to keep
the ac-coupling capacitors connected to analog inputs biased up at a normal DC level, thus avoiding the need for
them to charge up suddenly when the input is changed from being unselected to selected for connection to an
ADC PGA. This option is controlled in Page-0/Reg-20 and 23. The user should ensure this option is disabled
when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, since it
can corrupt the recorded input signal if left operational when an input is selected.
In most cases, the analog input pins on the TLV320AIC3106 should be ac-coupled to analog input sources, the
only exception to this generally being if an ADC is being used for DC voltage measurement. The ac-coupling
capacitor will cause a highpass filter pole to be inserted into the analog signal path, so the size of the capacitor
must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed
analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies
with the setting of the input level control, starting at approximately 20 k
with an input level control setting of 0-
dB, and increasing to approximately 80-k
when the input level control is set at –12 dB. For example, using a
0.1
μF ac-coupling capacitor at an analog input will result in a highpass filter pole of 80 Hz when the 0 dB input
level control setting is selected.
PASSIVE ANALOG BYPASS DURING POWERDOWN
Programming the TLV320AIC3106 to passive analog bypass occurs by configuring the output stage switches for
pass through. This is done by opening switches SW-L0, SW-L3, SW-R0, SW-R3 and closing either SW-L1 or
SW-L2 and SW-R1 or SW-R2. See Figure 33 Passive Analog Bypass Mode Configuration. Programming this
mode is done by writing to Page 0, Register 108.
Connecting MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0,
this action is done by writing a "1" to Page 0, Register 108, Bit D0. Connecting MIC2LP/LINE2LP input signal to
the LEFT_LOP pin is done by closing SW-L2 and opening SW-L0, this action is done by writing a "1" to Page 0,
Register 108, Bit D2. Connecting MIC1LM/LINE1LM input signal to the LEFT_LOM pin is done by closing SW-L4
and opening SW-L3, this action is done by writing a "1" to Page 0, Register 108, Bit D1. Connecting
MIC2LM/LINE2LM input signal to the LEFT_LOM pin is done by closing SW-L5 and opening SW-L3, this action
is done by writing a "1" to Page 0, Register 108, Bit D3.
Connecting MIC1RP/LINE1RP input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening SW-
R0, this action is done by writing a "1" to Page 0, Register 108, Bit D4. Connecting MIC2RP/LINE2RP input
signal to the RIGHT_LOP pin is done by closing SW-R2 and opening SW-R0, this action is done by writing a "1"
to Page 0, Register 108, Bit D6. Connecting MIC1RM/LINE1RM input signal to the RIGHT_LOM pin is done by
closing SW-R4 and opening SW-R3, this action is done by writing a "1" to Page 0, Register 108, Bit D5.
Connecting MIC2RM/LINE2RM input signal to the RIGHT_LOM pin is done by closing SW-R5 and opening SW-
R3, this action is done by writing a "1" to Page 0, Register 108, Bit D7. A diagram of the passive analog bypass
mode configuration can be seen in Figure 33.
In general, connecting two switches to the same output pin should be avoided, as this error will short two input
signals together, and would like cause distortion of the signal as the two signal are in contention, and poor
frequency response would also likely occur.
42
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Links: TLV320AIC3106-Q1
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