參數(shù)資料
型號(hào)： 6PAIC3106IRGZRQ1
廠商： Texas Instruments
文件頁數(shù)： 42/103頁
文件大小： 0K
描述： IC AUDIO CODEC STEREO 48-QFN
標(biāo)準(zhǔn)包裝： 1
類型： 立體聲音頻
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 是
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 92 / 102（差分），92 / 95（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 91 / 99（差分），91 / 92（單端）
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.1 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 48-VQFN 裸露焊盤（7x7）
包裝： 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面： 1077 (CN2011-ZH PDF)
其它名稱： 296-25253-6
MIC2RM/LINE2RM
MIC2RP /LINE2RP
LINE2RP
LINE2RM
MIC1RM/LINE1RM
MIC1RP /LINE1RP
LINE1RP
LINE1RM
MIC1LM/LINE1LM
MIC1LP /LINE1LP
LINE1LP
LINE1LM
MIC2LM/LINE2LM
MIC2LP /LINE2LP
LINE2LP
LINE2LM
LINE1LP
LINE2LM
LINE2LP
LINE1LM
SW-L0
SW-L3
SW-L1
SW-L2
SW-L4
SW-L5
LINE1RP
LINE2RM
LINE2RP
LINE1RM
SW-R0
SW-R3
SW-R1
SW-R2
SW-R4
SW-R5
RIGHT_LOP
RIGHT_LOM
LEFT_LOP
LEFT_LOM
SLAS663B – AUGUST 2009 – REVISED OCTOBER 2012
Figure 33. Passive Analog Bypass Mode Configuration
MICBIAS GENERATION
The TLV320AIC3106 includes a programmable microphone bias output voltage (MICBIAS), capable of providing
output voltages of 2.0 V or 2.5 V (both derived from the on-chip bandgap voltage) with 4-mA output current drive.
In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip switch, or it
can be powered down completely when not needed, for power savings. This function is controlled by register
programming in Page-0/Reg-25.
DIGITAL MICROPHONE CONNECTIVITY
The TLV320AIC3106 includes support for connection of a digital microphone to the device by routing the digital
signal directly into the ADC digital decimation filter, where it is filtered, downsampled, and provided to the host
processor over the audio data serial bus.
When digital microphone mode is enabled, the TLV320AIC3106 provides an oversampling clock output for use
by the digital microphone to transmit its data. The TLV320AIC3106 includes the capability to latch the data on
either the rising, falling, or both edges of this supplied clock, enabling support for stereo digital microphones.
In this mode, the oversampling ratio of the digital mic modulator can be programmed as 128, 64 or 32 times the
ADC sample rate, ADCFS. The GPIO1 pin will output the serial oversampling clock at the programmed rate.
TLV320AIC3106 latches the data input on GPIO2 as the Left and Right channel digital microphone data. For the
Left channel input, GPIO2 will be sampled on the rising edge of the clock, and for the Right channel input,
GPIO2 will be sampled on the falling edge of the clock. If a single digital mic channel is needed then the
corresponding ADC channel should be powered up, and the unused channel should be powered down. When
digital microphone mode is enabled, neither ADC can be used for digitizing analog inputs.
Configuring the digital microphone configuration set up is done by writing to Page 0, Register 107, bits D5-D4,
and Register 25, bits D5-D4.
Copyright 2009–2012, Texas Instruments Incorporated
43
Product Folder Links: TLV320AIC3106-Q1
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