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CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE
Figure 8-9. Format of Serial Bus Interface Control Register
(
μ
PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B,
78098B subseries,
μ
PD78070A) (2/2)
R/W
ACKE
Controls acknowledge signal output
0
Disables automatic output of acknowledge signal (output by ACKT is enabled)
1
Before completion
of transfer
Acknowledge signal is output in synchronization with falling edge of 9th clock
of SCK0 (automatically output when ACKE = 1)
After completion
of transfer
Acknowledge signal is output in synchronization with falling edge of SCK0
clock immediately after instruction that sets this bit to 1 has been executed
(automatically output when ACKE = 1). However, this bit is not automatically
cleared to 0 after acknowledge signal has been output.
R ACKD
Acknowledge detection
Clear condition (ACKD = 0)
Set condition (ACKD = 1)
Falling edge of SCK0 clock immediately after
busy mode has been released after execution
of transfer start instruction
When CSIE0 = 0
At RESET input
When acknowledge signal (ACK) is detected at
rising edge of SCK0 clock after completion of
transfer
R/W
Controls output of synchronization busy signal
0
Disables output of busy signal in synchronization with falling edge of SCK0 clock immediately after
instruction that clears this bit to 0 has been executed
1
Outputs busy signal at falling edge of SCK0 clock following acknowledge signal
Note
The busy mode can be released by starting serial interface transfer and receiving of an address signal.
However, the BSYE flag is not cleared to 0.
Remark
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
BSYE
Note