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CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE
Figure 8-9. Format of Serial Bus Interface Control Register
(
μ
PD78054, 78064, 78078, 78098, 780058, 780308, 78058F, 78064B, 78075B,
78098B subseries,
μ
PD78070A) (1/2)
R/W
RELT
Used to output bus release signal.
When RELT = 1, SO latch is set to 1. After SO latch has been set, this bit is automatically cleared to
0. It is also cleared to 0 when CSIE = 0.
R/W CMDT Used to output command signal.
When CMDT = 1, SO latch is cleared to 0. After SO latch has been cleared, this bit is automatically
cleared to 0. It is also cleared to 0 when CSIE0 = 0.
R
RELD
Clear condition (RELD = 0)
Bus release detection
Set condition (RELD = 1)
On execution of transfer start instruction
When bus release signal (REL) is detected
If values of SIO0 and SVA do not coincide when
address is received
When CSIE0 = 0
At RESET input
R CMDD
Command detection
Clear condition (CMDD = 0)
On execution of transfer start instruction
Set condition (CMDD = 1)
When command signal (CMD) is detected
When bus release signal (REL) is detected
When CSIE0 = 0
At RESET input
R/W
ACKT
Outputs acknowledge signal in synchronization with falling edge of SCK0 clock immediately after
instruction that sets this bit to 1 has been executed. After acknowledge signal has been output, this
bit is automatically cleared to 0. ACKE is cleared to 0.
This bit is also cleared to 0 when transfer of serial interface is started and when CSIE0 = 0.
Note
Bits 2, 3, and 6 (RELD, CMDD, and ACKD) are read-only bits.
Remarks 1.
Bits 0, 1, and 4 (RELD, CMDT, and ACKT) are cleared to 0 when they are read after data has been
set.
2.
CSIE0: Bit 7 of the serial operating mode register 0 (CSIM0)
7
6
5
4
3
2
Symbol
1
0
FF61H
RELT
SBIC
CMDT
CMDD RELD
ACKT
ACKE
ACKD
BSYE
Address
At reset
R/W
00H
R/W
Note