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CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER
5.3.2 Remote controller signal reception by PWM output and free running mode
Table 5-2 shows the valid pulse width when a remote controller signal is received by this program. <1> through
<6> below describes how each signal is processed.
Table 5-2. Valid Time of Input Signal
Signal Name
Output Time
Valid Time
Leader code (low)
9 ms
3 ms-10 ms
Leader code
Normal
4.5 ms
3 ms-5 ms
(high)
Repeat
2.25 ms
1.8 ms-3 ms
Custom/data
0
1.125 ms
0.5 ms-1.8 ms
code
1
2.25 ms
1.8 ms-2.5 ms
<1>
Leader code (low)
The value of the capture/compare register 01 (CR01) is stored to memory by an interrupt request that
occurs when the falling edge of INTP0 is detected.
The pulse width is measured from the difference between the values of CR01 and the capture/compare
register 00 (CR00) when the rising edge is generated.
<2>
Leader code (high)
The pulse width between the high levels of the leader code is measured by the falling-edge interrupt
request INTP0 and the count value of the timer.
<3>
Custom/data code
The pulse width of each 1 bit (1 cycle) is measured by the falling-edge interrupt request INTP0. After
the data of the 32nd bit has been loaded, the system tests if the inverted data and custom code coincide.
It also checks that there is no data of the 33rd bit.
<4>
Repeat code detection
When the high level of the leader code is less than 3 ms, the pulse width from output of the leader code
to the rising edge of the INTP0 is measured.
<5>
Valid period of repeat code
After the valid data has been input, the overflow flag (OVF0) of the 16-bit timer/event counter is tested
by the main program, and the repeat code valid time of 250 ms is measured.