33
CHAPTER 1 GENERAL
Table 1-12. Functional Outline of
μ
PD780058Y Subseries (1/2)
Item
Part Number
Mask ROM
Flash memory
24K bytes
32K bytes
40K bytes
48K bytes
60K bytes
60K bytes
Note 1
1024 bytes
32 bytes
None
1024 bytes
1024 bytes
Note 2
64K bytes
8 bits
×
8
×
4 banks
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s/12.8
μ
s (at 5.0 MHz)
122
μ
s (at 32.768 kHz)
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
Total
CMOS input
CMOS I/O
N-ch open-drain I/O : 4
: 68
: 2
: 62
8-bit resolution
×
8 channels
8-bit resolution
×
2 channels
3-wire serial I/O/2-wire serial I/O/I
2
C bus mode selectable
3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes)
: 1 channel
3-wire serial I/O/UART mode selectable (with time-division transfer function) : 1 channel
: 1 channel
16-bit timer/event counter : 1 channel
8-bit timer/event counter : 2 channels
Watch timer
Watchdog timer
: 1 channel
: 1 channel
3 (14-bit PWM output: 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with
main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
Notes 1.
The capacities of the flash memory can be changed by using a memory size select register (IMS).
2.
The internal expansion RAM capacity can be changed by using an internal expansion RAM size select
register (IXS).
Caution The
μ
PD780058Y subseries is under planning.
ROM
High-speed RAM
Buffer RAM
Expansion RAM
Memory space
General-purpose register
Minimum
With main
instruction
system clock
execution With subsystem
time
clock
Instruction set
I/O port
A/D converter
D/A converter
Serial interface
Timer
Timer output
Clock output
Internal
memory
μ
PD780053Y
μ
PD780054Y
μ
PD780055Y
μ
PD780056Y
μ
PD780058Y
μ
PD78F0058Y