5
CHAPTER 1 GENERAL
Table 1-1. Functional Outline of
μ
PD78054 Subseries (1/2)
Item
Part Number
Mask ROM
PROM
Mask ROM
PROM
16K bytes
24K bytes
32K bytes
32K bytes
Note 2
40K bytes
48K bytes
60K bytes
60K bytes
Note 3
512 bytes
1024 bytes
1024 bytes
Note 3
1024 bytes
1024 bytes
Note 3
32 bytes
None
1024 bytes
1024 bytes
Note 4
64K bytes
8 bits
×
8
×
4 banks
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s/12.8
μ
s (at 5.0 MHz)
122
μ
s (at 32.768 kHz)
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
Total
CMOS input
CMOS I/O
N-ch open-drain I/O : 4
: 69
: 2
: 63
8-bit resolution
×
8 channels
8-bit resolution
×
2 channels
3-wire serial I/O/SBI/2-wire serial I/O mode selectable
3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel
3-wire serial I/O/UART mode selectable
: 1 channel
: 1 channel
16-bit timer/event counter : 1 channel
8-bit timer/event counter : 2 channels
Watch timer
Watchdog timer
: 1 channel
: 1 channel
3 (14-bit PWM output: 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with
main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
Notes 1.
The
μ
PD78P054 is a PROM model of the
μ
PD78052, 78053, and 78054.
2.
The
μ
PD78P058 is a PROM model of the
μ
PD78055, 78056, and 78058.
3.
The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory
size select register (IMS).
4.
The internal expansion RAM capacity can be changed by using an internal expansion RAM size select
register (IXS).
ROM
High-speed RAM
Buffer RAM
Expansion RAM
Memory space
General-purpose register
Minimum
With main
instruction
system clock
execution With subsystem
time
clock
Instruction set
I/O port
A/D converter
D/A converter
Serial interface
Timer
Timer output
Clock output
μ
PD78052
μ
PD78053
μ
PD78054
μ
PD78P054
μ
PD78055
μ
PD78056
μ
PD78058
μ
PD78P058
Note 1
Note 2
Internal
memory