106
CHAPTER 5 APPLICATIONS OF 16-BIT TIMER/EVENT COUNTER
Figure 5-1. Format of Timer Clock Select Register 0
(
μ
PD78054, 78054Y, 78064, 78064Y, 78078, 78078Y, 780058, 780058Y, 780308,
780308Y, 78058F, 78058FY, 78064B, 78075B, 78075BY subseries,
μ
PD78070A,
78070AY)
TCL03 TCL02 TCL01 TCL00
Selects clock of PCL output
MCS = 1
MCS = 0
0
0
0
0
f
XT
(32.768 kHz)
0
1
0
1
f
XX
f
X
(5.0 MHz)
f
X
/2 (2.5 MHz)
0
1
1
0
f
XX
/2
f
X
/2 (2.5 MHz)
f
X
/2
2
(1.25 MHz)
0
1
1
1
f
XX
/2
2
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
1
0
0
0
f
XX
/2
3
f
X
/2
3
(625 kHz)
f
X
/2
4
(313 kHz)
1
0
0
1
f
XX
/2
4
f
X
/2
4
(313 kHz)
f
X
/2
5
(156 kHz)
1
0
1
0
f
XX
/2
5
f
X
/2
5
(156 kHz)
f
X
/2
6
(78.1 kHz)
1
0
1
1
f
XX
/2
6
f
X
/2
6
(78.1 kHz)
f
X
/2
7
(39.1 kHz)
1
1
0
0
f
XX
/2
7
f
X
/2
7
(39.1 kHz)
f
X
/2
8
(19.5 kHz)
Others
Setting prohibited
TCL06 TCL05 TCL04
Selects count clock of 16-bit timer register
MCS = 1
MCS = 0
0
0
0
TI00 (valid edge can be specified)
0
0
1
2f
XX
Setting prohibited
f
X
(5.0 MHz)
0
1
0
f
XX
f
X
(5.0 MHz)
f
X
/2 (2.5 MHz)
0
1
1
f
XX
/2
f
X
/2 (2.5 MHz)
f
X
/2
2
(1.25 MHz)
1
0
0
f
XX
/2
2
f
X
/2
2
(1.25 MHz)
f
X
/2
3
(625 kHz)
1
1
1
Watch timer output (INTTM3)
Others
Setting prohibited
CLOE
Controls PCL output
0
Disables output
1
Enables output
Cautions 1. The valid edge of the TI00/INTP0 pin is specified by the external interrupt mode register 0
(INTM0). The frequency of the sampling clock is selected by the sampling clock select register
(SCS).
2. To enable PCL output, set TCL00 through TCL03, and then set CLOE to 1 by using a 1-bit
memory manipulation instruction.
3. Read the count value from TM0, not from the capture/compare register 01(CR01), when TI00
is specified as the count clock of TM0.
4. Before writing new data to TCL0, stop the timer operation once.
7
6
5
4
3
2
Symbol
1
0
FF40H
TCL00
TCL0
TCL01
TCL03 TCL02
TCL04
TCL05
TCL06
CLOE
Address
At reset
R/W
00H
R/W