243
CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE
Figure 8-27. Communication Format of
μ
PD6252
(1) RANDOM WRITE
(2) CURRENT READ
(3) RANDOM READ
CS
SDA
SCL
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
WA
7
WA
6
WA
5
WA
4
WA
3
WA
2
WA
1
WA
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
2nd byte
WB flag output
Write is executed by making CS in low with SCL pin high.
WA is last written address + 1 and is retained
(current address) (issuance of STP).
WA input
Command input
Write data input (WA) (WA + 1) (WA + 2)
Internal WA
SDA mode
Starts by making CS pin high
when SCL pin is high
(issuance of STA).
WA retains input value until STP is
detected, and is incremented each time
1 byte is written in the internal write
cycle after STP has been detected.
WB flag is retained while eight
clocks are input to SCL pin.
Data of 1st byte is written to
memory addressed by WA.
IN
OUT
IN
WA + 1 to WA + 3
0
0
0
0
0
0
0
0
CURRENT ADDRESS
WA
CS
SDA
SCL
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
0
D
7
D
6
D
2
D
0
WB flag output
Current address
Command input
Read data (WA)
(WA + 1)
Internal WA
SDA mode
IN
OUT
OUT
WA + n + 1
1
0
0
0
0
0
0
0
CURRENT ADDRESS = WA
WA+n
(WA + 2) (WA + n)
Operation ends by making CS pin high with
SCL pin high. WA is last read address + 1 and
retained (current address) (issuance of STP)
WA+2
WA+1
D
1
1st byte
3rd byte
Operation ends if CS pin is made low with
SCL pin high (issuance of STP).
WA is last read address + 1 and retained.
CS
SDA
SCL
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
WA
7
WA
6
WA
5
WA
4
WA
3
WA
2
WA
1
WA
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
WB flag output
WA input
(WA)
Internal WA
SDA mode
IN
OUT
IN
WA + n + 1
1
1
0
0
0
0
0
0
CURRENT ADDRESS
WA
D
7
D
1
D
0
(WA+1) ··· (WA+n)
WB flag is retained while 8 clocks are input to SCL pin.
Starts by making CS pin high
with SCL pin high (issuance of STA).
Contents of WA are read as
data of first byte.
Contents of WA+1, ··· WA+n are
sequentially read each time 1 byte
has been read.
WA+1 WA+n
OUT