13
CHAPTER 1 GENERAL
Table 1-4. Functional Outline of
μ
PD78064Y Subseries
Item
Part Number
Mask ROM
16K bytes
24K bytes
32K bytes
512 bytes
1024 bytes
40
×
4 bits
64K bytes
8 bits
×
8
×
4 banks
0.4
μ
s/0.8
μ
s/1.6
μ
s/3.2
μ
s/6.4
μ
s/12.8
μ
s (at 5.0 MHz)
122
μ
s (at 32.768 kHz)
16-bit operation
Multiplication/division (8 bits
×
8 bits, 16 bits
÷
8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjustment, etc.
Total
CMOS input: 2
CMOS I/O
: 57
: 55
8-bit resolution
×
8 channels
Segment signal output : 40 max.
Common signal output : 4 max.
Bias
: 1/2 or 1/3 bias selectable
3-wire serial I/O/2-wire serial I/O/I
2
C bus mode selectable : 1 channel
3-wire serial I/O/UART mode selectable
: 1 channel
16-bit timer/event counter : 1 channel
8-bit timer/event counter : 2 channels
Watch timer
Watchdog timer
: 1 channel
: 1 channel
3 (14-bit PWM output: 1)
19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with
main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz)
1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz)
Internal: 12, external: 6
Internal: 1
1
Internal: 1, external: 1
V
DD
= 2.0 to 6.0 V
100-pin plastic QFP (fine pitch) (14
×
14 mm, resin thickness 1.45 mm)
100-pin plastic LQFP (fine pitch) (14
×
14 mm, resin thickness 1.4 mm)
100-pin plastic QFP (14
×
20 mm)
ROM
High-speed RAM
LCD display RAM
Memory space
General-purpose register
Minimum
With main
instruction
system clock
execution With subsystem
time
clock
Instruction set
I/O port
(including pins multiplexed
with segment signal output)
A/D converter
LCD controller/driver
Serial interface
Timer
Timer output
Clock output
Buzzer output
Vectored
Maskable
interrupt
Non-maskable
source
Software
Test input
Supply voltage
Package
μ
PD78062Y
μ
PD78063Y
μ
PD78064Y
Internal
memory