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XRT94L43
299
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
REV. 1.0.2
NOTE: The values for t0 through t11 can be found in Table 4. NOTE: Test Conditions: TA = 25°C, VCC = 3.3V±5% and 2.5V±5%, unless otherwise specified.
2.0
STS-12/STM-4 TELECOM BUS INTERFACE TIMING INFORMATION
FIGURE 12. SYNCHRONOUS MODE 4 - IDT3051/52 INTERFACE TIMING (READ CYCLE)
TABLE 4: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE
IDT3051/52 MODE
TIMING
DESCRIPTION
MIN.
TYP.
MAX.
t0
pCS_L low to Clock high
6
-
t1
pALE high to Clock high
1
-
t2
Clock high to pALE low
6
-
t3
Data setup time (WRITE cycle)
-
N/N
t4
Data hold time (WRITE cycle)
-
N/N
t5
Clock high to pRDY_L low
-
11
t6
Clock high to pWR_L high
6
-
t7
Clock high to Data valid (READ cycle)
-
N/N
t8
Clock high to pRDY_L high
-
11
t9
pRDY_L high to Data invalid
0
-
t10
Clock high to pRD_L high
11
-
t11
Clock high to pDBEN_L high
10
-
t
7
t
8
t
9
pCLK
pCS_L
pA[7:0]
pD[7:0]
pRdy_L
pWR_L
pRD_L
t
5
pDBEN_L
pALE
Address
t
10
t
11
Data