![](http://datasheet.mmic.net.cn/Exar-Corporation/XRT94L43IB-F_datasheet_100164/XRT94L43IB-F_300.png)
XRT94L43
294
REV. 1.0.2
SONET/SDH OC-12 TO 12XDS3/E3 MAPPER
NOTE: Test Conditions: TA = 25°C, VCC = 3.3V±5% and 2.5V±5%, unless otherwise specified.
1.2
MICROPROCESSOR INTERFACE TIMING - ASYNCHRONOUS MOTOROLA (68K) MODE
NOTE: The values for t0 through t7 can be found in Table 2. TABLE 1: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE, WHEN CONFIGURED TO OPERATE IN THE
INTEL ASYNCHRONOUS MODE
TIMING
DESCRIPTION
MIN.
TYP.
MAX.
t0
Address setup time to pALE low
6
-
t1
Address hold time to pALE low
6
-
t2
pRD_L, pWR_L pulse width
320
-
t3
Data setup time to pWR_L low
0
-
t4
Data hold time to pWR_L high
0
-
t5
pALE low to pRD_L, pWR_L low
5
-
t6
Data invalid from pRD_L high
7
-
t7
Data valid from pRDY_L low
-
0
FIGURE 7. ASYNCHRONOUS MODE 2 - MOTOROLA 68K PROGRAMMED I/O TIMING (WRITE CYCLE)
Address
Data
t
0
CS
ALE_AS
A[6:0]
D[7:0]
RD_DS
WR_R/W
RDY_DTACK
t
2
t
3
t
4
t
1