參數(shù)資料
型號: XRT86VL38IB484-F
廠商: Exar Corporation
文件頁數(shù): 4/160頁
文件大?。?/td> 0K
描述: IC LIU/FRAMER T1/E1/J1 8CH 484BG
標(biāo)準(zhǔn)包裝: 60
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-STBGA(23x23)
包裝: 托盤
XRT86VL38
96
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3
LCV Int Status
RUR/
WC
0
Line Code Violation Interrupt Status.
This Reset-Upon-Read bit field indicates whether or not the Receive T1 LIU
block has detected a Line Code Violation interrupt since the last read of this
register.
0 = Indicates no Line Code Violation have occurred since the last read of
this register.
1 = Indicates one or more Line Code Violation interrupt has occurred since
the last read of this register.
2
Rx LOF State
Change
RUR/
WC
0
Change in Receive Loss of Frame Condition Interrupt Status.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive Loss of Frame Condition” interrupt has occurred since the last
read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will generate
an interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the Loss of Frame
condition.
2. Whenever the Receive T1 Framer block clears the Loss of Frame
condition
0 = Indicates that the “Change in Receive Loss of Frame condition” inter-
rupt has not occurred since the last read of this register
1 = Indicates that the “Change in Receive Loss of Frame condition” inter-
rupt has occurred since the last read of this register
1
RxAIS State
Change
RUR/
WC
0
Change in Receive AIS Condition Interrupt Status.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive AIS Condition” interrupt has occurred since the last read of this
register.
If this interrupt is enabled, then the Receive T1 Framer block will generate
an interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the AIS condition.
2. Whenever the Receive T1 Framer block clears the AIS condition
0 = Indicates that the “Change in Receive AIS condition” interrupt has not
occurred since the last read of this register
1 = Indicates that the “Change in Receive AIS condition” interrupt has
occurred since the last read of this register
0
RxYEL State
Change
RUR/
WC
0
Change in Receive Yellow Alarm Interrupt Status.
This Reset-Upon-Read bit field indicates whether or not the “Change in
Receive Yellow Alarm Condition” interrupt has occurred since the last read
of this register.
If this interrupt is enabled, then the Receive T1 Framer block will generate
an interrupt in response to either one of the following conditions.
1. Whenever the Receive T1 Framer block declares the Yellow Alarm
condition.
2. Whenever the Receive T1 Framer block clears the Yellow Alarm
condition
0 = Indicates that the “Change in Receive Yellow Alarm condition” interrupt
has not occurred since the last read of this register
1 = Indicates that the “Change in Receive Yellow Alarm condition” interrupt
has occurred since the last read of this register
TABLE 82: ALARM & ERROR INTERRUPT STATUS REGISTER (AEISR)
HEX ADDRESS: 0XnB02
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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