TABLE
參數(shù)資料
型號： XRT86VL38IB484-F
廠商： Exar Corporation
文件頁數(shù)： 148/160頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 8CH 484BG
標(biāo)準(zhǔn)包裝： 60
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 484-BGA
供應(yīng)商設(shè)備封裝： 484-STBGA（23x23）
包裝： 托盤
XRT86VL38
83
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
TABLE 62: PMON RECEIVE LINE CODE VIOLATION COUNTER MSB (RLCVCU)
HEX ADDRESS: 0Xn900
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
RLCVC[15]
RUR
0
Performance Monitor “Receive Line Code Violation” 16-bit
Counter - Upper Byte:
These RESET-upon-READ bits, along with that within the PMON
Receive Line Code Violation Counter Register LSB combine to
reflect the cumulative number of instances that Line Code Violation
has been detected by the Receive T1 Framer block since the last
read of this register.
This register contains the Most Significant byte of this 16-bit of the
Line Code Violation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
RLCVC[14]
RUR
0
5
RLCVC[13]
RUR
0
4
RLCVC[12]
RUR
0
3
RLCVC[11]
RUR
0
2
RLCVC[10]
RUR
0
1
RLCVC[9]
RUR
0
RLCVC[8]
RUR
0
TABLE 63: PMON RECEIVE LINE CODE VIOLATION COUNTER LSB (RLCVCL)
HEX ADDRESS: 0Xn901
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
RLCVC[7]
RUR
0
Performance Monitor “Receive Line Code Violation” 16-bit
Counter - Lower Byte:
These RESET-upon-READ bits, along with that within the PMON
Receive Line Code Violation Counter Register MSB combine to
reflect the cumulative number of instances that Line Code Violation
has been detected by the Receive T1 Framer block since the last
read of this register.
This register contains the Least Significant byte of this 16-bit of the
Line Code Violation counter.
NOTE: For all 16-bit wide PMON registers, user must read the MSB
counter first before reading the LSB counter in order to read
the accurate PMON counts. To clear PMON count, user
must read the MSB counter first before reading the LSB
counter in order to clear the PMON count.
6
RLCVC[6]
RUR
0
5
RLCVC[5]
RUR
0
4
RLCVC[4]
RUR
0
3
RLCVC[3]
RUR
0
2
RLCVC[2]
RUR
0
1
RLCVC[1]
RUR
0
RLCVC[0]
RUR
0
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