TABLE 9: M
參數(shù)資料
型號(hào)： XRT83VSH38IB-F
廠商： Exar Corporation
文件頁數(shù)： 56/76頁
文件大小： 0K
描述： IC LIU SH T1/E1/J1 8CH 225BGA
標(biāo)準(zhǔn)包裝： 84
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 8/8
規(guī)程： T1，E1，J1
電源電壓： 3.14 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
其它名稱： 1016-1484
XRT83VSH38IB-F-ND
XRT83VSH38
II
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.1.0
TABLE 9: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS........................................................................................... 29
4.4 TAOS (TRANSMIT ALL ONES) ...................................................................................................................... 29
FIGURE 18. TAOS (TRANSMIT ALL ONES) ............................................................................................................................................ 29
4.5 TRANSMIT DIAGNOSTIC FEATURES .......................................................................................................... 29
4.5.1 ATAOS (AUTOMATIC TRANSMIT ALL ONES)......................................................................................................... 29
FIGURE 19. SIMPLIFIED BLOCK DIAGRAM OF THE ATAOS FUNCTION ..................................................................................................... 30
4.5.2 QRSS/PRBS GENERATION....................................................................................................................................... 30
TABLE 10: RANDOM BIT SEQUENCE POLYNOMIALS................................................................................................................................30
4.5.3 T1 SHORT HAUL LINE BUILD OUT (LBO) ............................................................................................................... 30
TABLE 11: SHORT HAUL LINE BUILD OUT.............................................................................................................................................. 30
4.5.4 ARBITRARY PULSE GENERATOR FOR T1 AND E1 ............................................................................................... 30
FIGURE 20. ARBITRARY PULSE SEGMENT ASSIGNMENT ......................................................................................................................... 31
4.6 DMO (DIGITAL MONITOR OUTPUT) ............................................................................................................. 31
4.7 LINE TERMINATION (TTIP/TRING) ............................................................................................................... 31
FIGURE 21. TYPICAL CONNECTION DIAGRAM USING INTERNAL TERMINATION ......................................................................................... 31
5.0 T1/E1 APPLICATIONS .........................................................................................................................32
5.1 LOOPBACK DIAGNOSTICS .......................................................................................................................... 32
5.1.1 LOCAL ANALOG LOOPBACK .................................................................................................................................. 32
FIGURE 22. SIMPLIFIED BLOCK DIAGRAM OF LOCAL ANALOG LOOPBACK................................................................................................ 32
5.1.2 REMOTE LOOPBACK ................................................................................................................................................ 32
FIGURE 23. SIMPLIFIED BLOCK DIAGRAM OF REMOTE LOOPBACK .......................................................................................................... 32
5.1.3 DIGITAL LOOPBACK ................................................................................................................................................. 33
FIGURE 24. SIMPLIFIED BLOCK DIAGRAM OF DIGITAL LOOPBACK ........................................................................................................... 33
5.1.4 DUAL LOOPBACK ..................................................................................................................................................... 33
FIGURE 25. SIMPLIFIED BLOCK DIAGRAM OF DUAL LOOPBACK ............................................................................................................... 33
5.2 LINE CARD REDUNDANCY ........................................................................................................................... 34
5.2.1 1:1 AND 1+1 REDUNDANCY WITHOUT RELAYS .................................................................................................... 34
5.2.2 TRANSMIT INTERFACE WITH 1:1 AND 1+1 REDUNDANCY .................................................................................. 34
FIGURE 26. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR 1:1 AND 1+1 REDUNDANCY ................................................ 34
5.2.3 RECEIVE INTERFACE WITH 1:1 AND 1+1 REDUNDANCY..................................................................................... 35
FIGURE 27. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR 1:1 AND 1+1 REDUNDANCY .................................................. 35
5.2.4 N+1 REDUNDANCY USING EXTERNAL RELAYS ................................................................................................... 36
5.2.5 TRANSMIT INTERFACE WITH N+1 REDUNDANCY ................................................................................................ 36
FIGURE 28. SIMPLIFIED BLOCK DIAGRAM OF THE TRANSMIT INTERFACE FOR N+1 REDUNDANCY ............................................................ 36
5.2.6 RECEIVE INTERFACE WITH N+1 REDUNDANCY ................................................................................................... 37
FIGURE 29. SIMPLIFIED BLOCK DIAGRAM OF THE RECEIVE INTERFACE FOR N+1 REDUNDANCY .............................................................. 37
5.3 POWER FAILURE PROTECTION .................................................................................................................. 38
5.4 OVERVOLTAGE AND OVERCURRENT PROTECTION ............................................................................... 38
5.5 NON-INTRUSIVE MONITORING .................................................................................................................... 38
FIGURE 30. SIMPLIFIED BLOCK DIAGRAM OF A NON-INTRUSIVE MONITORING APPLICATION ..................................................................... 38
6.0 MICROPROCESSOR INTERFACE ......................................................................................................39
6.1 SERIAL MICROPROCESSOR INTERFACE BLOCK (BGA PACKAGE ONLY) ........................................... 39
FIGURE 31. SIMPLIFIED BLOCK DIAGRAM OF THE SERIAL MICROPROCESSOR INTERFACE ........................................................................ 39
6.1.1 SERIAL TIMING INFORMATION ................................................................................................................................ 39
FIGURE 32. TIMING DIAGRAM FOR THE SERIAL MICROPROCESSOR INTERFACE ....................................................................................... 39
6.1.2 24-BIT SERIAL DATA INPUT DESCRITPTION ......................................................................................................... 40
6.1.3 ADDR[7:0] (SCLK1 - SCLK8) ..................................................................................................................................... 40
6.1.4 R/W (SCLK9)............................................................................................................................................................... 40
6.1.5 DUMMY BITS (SCLK10 - SCLK16) ............................................................................................................................ 40
6.1.6 DATA[7:0] (SCLK17 - SCLK24) ................................................................................................................................. 40
6.1.7 8-BIT SERIAL DATA OUTPUT DESCRIPTION ......................................................................................................... 40
FIGURE 33. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE ....................................................................................... 41
TABLE 12: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) ...................................... 41
6.2 PARALLEL MICROPROCESSOR INTERFACE BLOCK .............................................................................. 42
TABLE 13: SELECTING THE MICROPROCESSOR INTERFACE MODE .......................................................................................................... 42
FIGURE 34. SIMPLIFIED BLOCK DIAGRAM OF THE MICROPROCESSOR INTERFACE BLOCK ........................................................................ 42
6.3 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 43
TABLE 14: XRT83VSH38 MICROPROCESSOR INTERFACE SIGNALS THAT EXHIBIT CONSTANT ROLES IN BOTH INTEL AND MOTOROLA MODES43
TABLE 15: INTEL MODE: MICROPROCESSOR INTERFACE SIGNALS........................................................................................................... 43
TABLE 16: MOTOROLA MODE: MICROPROCESSOR INTERFACE SIGNALS ................................................................................................. 44
6.4 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 45
FIGURE 35. INTEL P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS .................................................. 46
TABLE 17: INTEL MICROPROCESSOR INTERFACE TIMING SPECIFICATIONS .............................................................................................. 46
6.5 MOTOROLA MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) .................................................... 47
FIGURE 36. MOTOROLA 68K P INTERFACE SIGNALS DURING PROGRAMMED I/O READ AND WRITE OPERATIONS .................................. 48
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XRT83VSH38IB-F 制造商:Exar Corporation 功能描述:T1/E1 LIU IC
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