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參數(shù)資料
| 型號： | XRD98L59AIGTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 18/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD DIGITIZER 10BIT 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
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25
Rev. 2.00
XRD98L59
Digital Noise Supression (DNS Filter)
To activate the DNS mode, a "1" is written to DNS1 bit in
the Calibration register (bit D2 of Serial Interface Register
#5). By default the DNS mode is active.
In DNS mode, the user has the option to select narrow
band or wide band Noise Suppression Filters by setting
DNS0 bit to a "1" (narrow) or "0" (wide) respectively. Best
performance is achieved by setting DNS1 = "1" and
DNS0 = "0".
Hold Mode
The purpose of this mode is to prevent any changes in the
Fine or Coarse accumulators. The idea is to first run the
calibration normaly so the Fine and Coarse accumulators
converge on the programmed Target Offset Code. Then,
just before acquiring the final image data, activate the
Hold mode. This will ensure the black level offset of the
CDS/PGA does not change while the final image is being
transferred out of the CCD. Once the image has been
acquired from the CCD, turn off the Hold mode so the chip
can continue to compensate for any changes in offset
due to temperature drift or other effects.
To activate the Hold mode write a 1 to the CAL Hold bit
in the Calibration register (bit D4 of Serial Interface
Register #5). By default the Hold mode is not active.
Manual Mode
The purpose of this mode is to disable the automatic
calibration feature. In the Manual mode, the Coarse
accumulator is programmed by writing to the CDAC
register, the Fine accumulator is programmed by writing
to the FDAC register. The Fine accumulator is a 10 bit
register, but the Serial interface registers are only 8 bits
wide. As shown in the Serial Interface Register Address
Map, two serial interface registers are concatenated to
provide 10 bits to the Fine accumulator.
To activate the Manual mode write a 1 to the ManDAC bit
in the Calibration register (bit D0 of Serial Interface
Register #5). By default the Manual mode is not active.
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參數(shù)描述 |
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| XRD98L61 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
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| XRD98L61AIV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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