參數(shù)資料
型號(hào)： XRD98L59AIGTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 10/37頁(yè)
文件大小： 0K
描述： IC CCD DIGITIZER 10BIT 28TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
XRD98L59
18
Rev. 2.00
Figure 11. End of Line OB Pixels Used for
Line Calibration Mode on a Typical CCD Array
Active Pixels
End of LIne
OB
Calibration
Pixels
LINE CALIBRATION MODE
Line calibration mode calibrates during the OB pixel
output from the CCD at the end of every line. Figure 11,
shows the outline of a typical CCD area array. The
active (white) pixels are shown with the OB (shaded)
pixels around the edges. The OB pixels used in line
calibration are identified below in Figure 11 as the dark
shaded OB pixels on the right hand side of the array.
Line Timing: CLAMP and CAL
CLAMP & CAL Line Timing
(SDI address = 0011, D4 = 1)
The timing needed for Line Calibration Mode is shown in
Figure 12. The timing signal CAL gates the XRD98L59’s
auto-calibration logic. CAL is active during the end of
line OB pixels.
Most timing generators (TG’s) have signals that define
the start of line and end of line OB pixels on the CCD
array. CAL should always be active on start or the end
of line that defines the greatest number of OB pixels
possible.
The more OB pixels that the XRD98L59 can
use for its auto-calibration, the faster it can achieve and
maintain calibration. CAL and CLAMP must never be
active at the same time. CLAMP is used to set the
input DC bias voltage. (See Figure 5).
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