參數(shù)資料
型號(hào)： XRD98L59AIGTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 14/37頁(yè)
文件大小： 0K
描述： IC CCD DIGITIZER 10BIT 28TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 10
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
21
Rev. 2.00
XRD98L59
End of Line N
Start of Line N+1
Active Video
Pixels
OB Pixels
Vertical Shift
Dummy &
OB Pixels
CAL
Internal
D C Restore Time
CCD
Si g nal
Active Video Pixels
t
CAL (min 5 Pixels)
4 Pixels
(D1 = 0)
CLAMP
Internal Black Level
Calibration T i m e
t
CAL - 4 Pixels
Figure 13a. Example of Vertical Shift Reject Timing using the CLAMP input while in “CAL ONLY”
Line Calibration Mode. (CAL and CLAMP Polarity are Serial Port Programmable)
SDI = 0011 000 0000
÷
è
+
=
32
256
6
]
[
Code
dB
Gain
PROGRAMMABLE GAIN AMPLIFIER (PGA)
PGA1 provides gains of 0dB, 8dB & 16dB (1x, 2.5x, and
6.25x). The gain transitions occur at PGA gain codes 64d
and 128d (40h & 80h). PGA2 provides gain from 6dB to
22dB (2x to 12.5x) with 0.125dB steps. The combined
PGA blocks provide a programmable gain range of 32dB.
The minimum gain (code 00h) is 6dB. The maximum gain
(code FFh) is 38dB. The following equation can be used
to compute PGA gain from the gain code:
where
Code is the 8 bit value (0 to 255) programmed in
the serial interface Gain register. Due to device
mismatch the gain steps at codes 63 - 64 and 127 -
128 may not be monotonic.
ANALOG TO DIGITAL CONVERTER (ADC)
The analog-to-digital converter is based upon a two-step
sub-ranging flash converter architecture with a built in
track and hold input stage. The ADC conversion is
controlled by an internally generated signal, ADCLK (see
Figure 10). The ADC tracks the output of the PGA while
ADCLK is high and holds when ADCLK is low. This allows
maximum time for the PGA output to settle to its final
value before being sampled. The conversion is then
performed and the parallel output is updated, after a 2.5
cycle pipeline delay, on the edge of
φ2. The pipeline delay
of the entire XRD98L59 is 4 clock cycles.
The ADC reference levels, VRT & VRB, are set by an
internal resistor divider between VDD and GND. The
divider provides VRB=VDD/10 and VRT=VDD/1.3. To
maximize the performance of the XRD98L59, VRT &
VRB should have high frequency by-pass capacitors to
AGND. The value of these by-pass capacitors will affect
the time required for the reference to charge up and settle
after power down mode. Using 0.01uF capacitors will
give about 40
s settling time for full accuracy.
The ADC output bus is equipped with a high impedance
capability which is controlled by OE bit in the serial
interface control register. The outputs are enabled when
the OE bit is high, and go into high impedance mode when
the OE bit is low.
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