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參數(shù)資料
| 型號(hào)： | XR17V358IB-E8-EVB |
| 廠商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 6/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR XR17V358-E8 |
| 產(chǎn)品培訓(xùn)模塊： | PCIe UARTs UART Product Overview |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 接口，UART |
| 嵌入式： | 否 |
| 已用 IC / 零件： | XR17V358 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA |
| 其它名稱： | 1016-1296 |
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XR17V358
14
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
NOTE: EWR=Read/Write from external EEPROM. RWR=Read/Write. RO= Read Only. RWC=Read/Write-Clear.
1.2
EEPROM Interface
The V358 provides an interface to an Electrically Erasable Programmable Read Only Memory (EEPROM). The
EEPROM must be a 93C46-like device, with its memory configured as 16-bit words. This interface is provided
in order to program the registers in the PCI Configuration Space of the PCI UART during power-up. The
EEPROM must be organized into address/data pairs. The first word of the pair is the address and the second
word is the data. Table 2 below shows the format of the 16-bit address:
TABLE 2: EEPROM ADDRESS BIT DEFINITIONS
BIT(S)
DEFINITION
15
Parity Bit - Odd parity over entire address/data pair
If there is a parity error, it will be reported in bit-3 of the REGB register in
the Device Configuration Registers (offset 0x08E).
14
Final Address
If 1, this will be the last data to be read.
If 0, there will be more data to be read after this.
13:8
Reserved - Bits must be ’0’
7:0
Target Address - See
Table 3 shows the Target Addresses available for programming into bits 7:0 of the 16-bit address word. All
other Target Addresses are reserved and must not be used.
TABLE 3: TARGET ADDRESS FOR EEPROM VALUES
TARGET ADDRESS
DATA
EXAR DEFAULT
0x00
Vendor ID
0x13A8
0x01
Device ID
0x0358 - No slave
0x4358 - XR17V354 slave present
0x8358 - XR17V358 slave present
0x02
Class Code [7:0]
lower 8-bits are reserved
0x0200
0x03
Class Code [23:8]
0x0700
0x04
Subsystem Vendor ID
0x0000
0x05
Subsystem ID
0x0000
The second 16-bit word of the address/data pair is the data. The default values are shown in Table 3. The
address/data pairs can be in any order. Only the contents which need to be changed from the Exar defaults
need to be included in the EEPROM.
0x104-
0x113
31:0
RO
Not implemented or not applicable (return zeros)
0x00000000
0x114
31:0
RO
VC Offset 0x4
0x8000000FF
TABLE 1: PCI LOCAL BUS CONFIGURATION SPACE REGISTERS
ADDRESS
OFFSET
BITS
TYPE
DESCRIPTION
RESET VALUE
(HEX OR BINARY)
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