REV. 1.0.4 IER[1]: TX Ready Interrupt Enable In non-FIFO mode, a TX interrupt is issued whe" />
參數(shù)資料
型號： XR17V358IB-E8-EVB
廠商： Exar Corporation
文件頁數(shù)： 46/68頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V358-E8
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V358
已供物品： 板
相關(guān)產(chǎn)品： 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱： 1016-1296
XR17V358
50
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
IER[1]: TX Ready Interrupt Enable
In non-FIFO mode, a TX interrupt is issued whenever the THR is empty. In the FIFO mode, an interrupt is
issued twice: once when the number of bytes in the TX FIFO falls below the programmed trigger level and
again when the TX FIFO becomes empty. When autoRS485 mode is enabled (FCTR bit [5] = 1), the second
interrupt is delayed until the transmitter (both the TX FIFO and the TX Shift Register) is empty.
Logic 0= Disable Transmit Ready Interrupt (default).
Logic 1 = Enable Transmit Ready Interrupt.
IER[0]: RX Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when
the receive FIFO has reached the programmed trigger level in the FIFO mode.
Logic 0 = Disable the receive data ready interrupt (default).
Logic 1 = Enable the receiver data ready interrupt.
4.5
Interrupt Status Register (ISR) - Read Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others queue up for next
service. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt Source
Table, Table 15, shows the data values (bit [5:0]) for the six prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
4.5.1
Interrupt Generation:
LSR is by any of the LSR bits [4:1]. See IER bit [2] description on the previous page.
RXRDY is by RX trigger level.
RXRDY Time-out is by a 4-char plus 12 bits delay timer.
TXRDY is by TX trigger level or TX FIFO empty (or transmitter empty in auto RS-485 control).
MSR is by any of the MSR bits [3:0].
Receive Xoff/Xon/Special character is by detection of a Xoff, Xon or Special character.
CTS#/DSR# is when its transmitter toggles the input pin (from LOW to HIGH) during auto CTS/DSR flow
control enabled by EFR bit [7] and selection on MCR bit [2].
RTS#/DTR# is when its receiver toggles the output pin (from LOW to HIGH) during auto RTS/DTR flow
control enabled by EFR bit [6] and selection on MCR bit [2].
Wake-up indicator is when the UART wakes up from the sleep mode.
4.5.2
Interrupt Clearing:
LSR interrupt is cleared by a read to the LSR register.
RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.
RXRDY Time-out interrupt is cleared by reading RHR.
TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
MSR interrupt is cleared by a read to the MSR register.
Xoff/Xon interrupt is cleared by reading ISR.
Special character interrupt is cleared by a read to ISR.
RTS#/DTR# and CTS#/DSR# status change interrupts are cleared by a read to the MSR register.
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