參數(shù)資料
型號： XR17V358IB-E8-EVB
廠商： Exar Corporation
文件頁數(shù)： 26/68頁
文件大?。?/td> 0K
描述： EVAL BOARD FOR XR17V358-E8
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
UART Product Overview
標(biāo)準(zhǔn)包裝： 1
主要目的： 接口，UART
嵌入式： 否
已用 IC / 零件： XR17V358
已供物品： 板
相關(guān)產(chǎn)品： 1016-1294-ND - IC UART PCIE OCTAL 176FPBGA
其它名稱： 1016-1296
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+3
Receive Data Byte n+2
Receive Data Byte n+1
Receive Data Byte n+0
PCI Bus
Data Bit-0
Channel 0 to 7 Receive Data in 32-bit alignment through the Configuration Register Address
0x0100, 0x0500, 0x0900, 0x0D00, 0x1100, 0x1500, 0x1900 and 0x1D00
XR17V358
32
HIGH PERFORMANCE OCTAL PCI EXPRESS UART
REV. 1.0.4
2.1.2
Special Rx FIFO Data Unloading at locations 0x0200, 0x0600, 0x0A00, 0x0E00, 0x1200,
0x1600, 0x1A00, and 0x1E00
The XR17V358 also provides the same RX FIFO data along with the LSR status information of each byte side-
by-side, at locations 0x0200 (channel 0), 0x0200 (channel 1), 0x0A00 (channel 2), ....., 0x1E00 (channel 7).
The Status and Data bytes must be read in 16 or 32 bits format to maintain data integrity. The following tables
show this clearly.
READ RX FIFO,
WITH LSR
ERRORS
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Read n+0 to n+1
FIFO Data n+1
LSR n+1
FIFO Data n+0
LSR n+0
Read n+2 to n+3
FIFO Data n+3
LSR n+3
FIFO Data n+2
LSR n+2
Etc
PCI Bus
Data Bit-31
B7 B6 B5 B4 B3 B2 B1 B0
Receive Data Byte n+1
Line Status Register n+1
Receive Data Byte n+0
Line Status Register n+0
PCI Bus
Data Bit-0
Channel 0 to 7 Receive Data with Line Status Register in 32-bit alignment through the Configuration
Register Address 0x0200, 0x0600, 0x0A00, 0x0E00, 0x1200, 0x1600, 0x1A00 and 0x1E00
2.1.3
Tx FIFO Data Loading at locations 0x100, 0x500, 0x900, 0xD00, 0x1100, 0x1500, 0x1900, and
0x1D00
The TX FIFO data can be loaded 32-bit (4 bytes) at a time at memory locations 0x0100 (channel 0), 0x0500
(channel 1), 0x0900 (channel 2), ............, 0x1900 (channel 6) and 0x1D00 (channel 7).
WRITE TX FIFO
BYTE 3
BYTE 2
BYTE 1
BYTE 0
Write n+0 to n+3
FIFO Data n+3
FIFO Data n+2
FIFO Data n+1
FIFO Data n+0
Write n+4 to n+7
FIFO Data n+7
FIFO Data n+6
FIFO Data n+5
FIFO Data n+4
Etc.
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