REV. 1.0.3 HIGH PERFORMANCE QUAD PCI-EXPRESS UART FCTR[5]: Auto RS485 Enable Auto RS485 half duplex control enable/disable. RTS# or" />
參數(shù)資料
型號： XR17V354IB176-F
廠商： Exar Corporation
文件頁數(shù)： 55/66頁
文件大小： 0K
描述： IC UART PCIE 256B QUAD 176FPBGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
標(biāo)準(zhǔn)包裝： 160
特點： *
通道數(shù)： 4，QUART
FIFO's： 256 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 176-LFBGA
供應(yīng)商設(shè)備封裝： 176-FPBGA（13x13）
包裝： 托盤
其它名稱： 1016-1472
XR17V354IB176-F-ND
XR17V354
59
REV. 1.0.3
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
FCTR[5]: Auto RS485 Enable
Auto RS485 half duplex control enable/disable. RTS# or DTR# can be selected as the control output via MCR
bit-2. Note that this feature has precedence over the Auto RTS/DTR flow control feature (EFR bit-6).
Therefore, the Auto RTS/DTR flow control feature will not have any effect when the Auto RS485 Half-Duplex
Direction Control feature is enabled.
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
(THR) becomes empty. Transmit Shift Register (TSR) may still be shifting data bit out.
Logic 1 = Enable Auto RS485 half duplex direction control. RTS#/DTR# output changes from HIGH to LOW
when finished sending the last stop bit of the last character out of the TSR register. It changes from LOW to
HIGH when a data byte is loaded into the THR or transmit FIFO. The change to HIGH occurs prior sending
the start-bit. It also changes the transmitter interrupt from transmit holding to transmit shift register (TSR)
empty. If software flow control is enabled, the RTS#/DTR# output will not change if the TX FIFO is empty
and the RX FIFO level generates an XON or XOFF character to be transmitted.
FCTR[4]: Infrared RX Input Logic Select
Logic 0 = Select RX input as active HIGH encoded IrDA data, normal, (default).
Logic 1 = Select RX input as active LOW encoded IrDA data, inverted.
FCTR [3:0] - Auto RTS/DTR Flow Control Hysteresis Select
These bits select the auto RTS/DTR flow control hysteresis and only valid when TX and RX Trigger Table-D is
selected (FCTR bit [7:6] are set to logic 1). The RTS/DTR hysteresis is referenced to the RX FIFO trigger level.
After reset, these bits are set to logic 0 selecting the next FIFO trigger level for hardware flow control. Table 19
below shows the 16 selectable hysteresis levels.
TABLE 19: 16 SELECTABLE HYSTERESIS LEVELS WHEN TRIGGER TABLE-D IS SELECTED
FCTR BIT [3]
FCTR BIT [2]
FCTR BIT [1]
FCTR BIT [0]
RTS/DTR HYSTERESIS
(CHARACTERS)
0
1
+/- 4
0
1
0
+/- 6
0
1
+/- 8
0
1
0
+/- 8
0
1
0
1
+/- 16
0
1
0
+/- 24
0
1
+/- 32
1
0
+/- 12
1
0
1
+/- 20
1
0
+/- 28
1
+/- 36
1
0
+/- 40
1
0
1
+/- 44
1
0
1
0
+/- 48
1
0
1
+/- 52
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