REV. 1.0.3 HIGH PERFORMANCE QUAD PCI-EXPRESS UART D3 E14 I/O Expansion Interface Data 3. The trace capacitance between the master an" />
參數(shù)資料
型號: XR17V354IB176-F
廠商: Exar Corporation
文件頁數(shù): 45/66頁
文件大?。?/td> 0K
描述: IC UART PCIE 256B QUAD 176FPBGA
產(chǎn)品培訓模塊: PCIe UARTs
標準包裝: 160
特點: *
通道數(shù): 4,QUART
FIFO's: 256 字節(jié)
規(guī)程: RS485
電源電壓: 3.3V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 176-LFBGA
供應(yīng)商設(shè)備封裝: 176-FPBGA(13x13)
包裝: 托盤
其它名稱: 1016-1472
XR17V354IB176-F-ND
XR17V354
5
REV. 1.0.3
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
D3
E14
I/O
Expansion Interface Data 3. The trace capacitance between the master and
slave device must be less than 25pF.
D2
D15
I/O
Expansion Interface Data 2. The trace capacitance between the master and
slave device must be less than 25pF.
D1
E13
I/O
Expansion Interface Data 1. The trace capacitance between the master and
slave device must be less than 25pF.
D0
C15
I/O
Expansion Interface Data 0 (LSB). The trace capacitance between the master
and slave device must be less than 25pF.
SEL
G13
I/O
Expansion Interface Read/Write Select. This is the the read/write select input
in the slave mode. This is the read/write select output in the master mode.
This pin must be left unconnected if there is no slave device. The trace
capacitance between the master and slave device must be less than 25pF.
INT
D14
I/O
Expansion Interface Interrupt. This is the expansion interface interrupt output
in the slave mode. This is the expansion interface interrupt input in the mas-
ter mode. This pin must be left unconnected if there is no slave device. The
trace capacitance between the master and slave device must be less than
25pF.
PRES
H14
I
Slave Present. In master mode, connect this pin to VCC if there is a slave
device present. Connect this pin to GND to disable access to the slave
device (slave device may or may not be present). In slave mode, this pin
should be connected to GND.
MPIO SIGNALS
MPIO0
C1
I/O
Multi-purpose input/output 0. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
MPIO1
D2
I/O
Multi-purpose input/output 1. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO2
D1
I/O
Multi-purpose input/output 2. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO3
E3
I/O
Multi-purpose input/output 3. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO4
E2
I/O
Multi-purpose input/output 4. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO5
E1
I/O
Multi-purpose input/output 5. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO6
F3
I/O
Multi-purpose input/output 6. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO7
L3
I/O
Multi-purpose input/output 7. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
MPIO8
M2
I/O
Multi-purpose input/output 8. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT
MPIO9
N1
I/O
Multi-purpose input/output 9. The function of this pin is defined thru the Con-
figuration Register MPIOSEL, MPIOLVL, MPIOINV, MPIO3T and MPIOINT.
PIN DESCRIPTIONS
NAME
PIN #TYPE
DESCRIPTION
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