REV. 1.0.3 3.0 UART There are 4 UARTs channel [3:0] in the V354. Each has its own 256-byte o" />
參數(shù)資料
型號： XR17V354IB176-F
廠商： Exar Corporation
文件頁數(shù)： 26/66頁
文件大?。?/td> 0K
描述： IC UART PCIE 256B QUAD 176FPBGA
產(chǎn)品培訓模塊： PCIe UARTs
標準包裝： 160
特點： *
通道數(shù)： 4，QUART
FIFO's： 256 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 176-LFBGA
供應商設備封裝： 176-FPBGA（13x13）
包裝： 托盤
其它名稱： 1016-1472
XR17V354IB176-F-ND
XR17V354
32
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
REV. 1.0.3
3.0 UART
There are 4 UARTs channel [3:0] in the V354. Each has its own 256-byte of transmit and receive FIFO, a set of
16550 compatible control and status registers, and a baud rate generator for individual channel data rate
setting. Eight additional registers per UART were added for the EXAR enhanced features.
3.1
Programmable Baud Rate Generator with Fractional Divisor
Each UART has its own Baud Rate Generator (BRG) with a prescaler for the transmitter and receiver. The
prescaler is controlled by a software bit in the MCR register. The MCR register bit [7] sets the prescaler to
divide the internal 125MHz clock (master) or 62.5MHz clock (slave) by 1 or 4. The output of the prescaler
clocks to the BRG. The BRG further divides this clock by a programmable divisor between 1 and (216 - 0.0625)
in increments of 0.0625 (1/16) to obtain a 16X, 8X or 4X sampling clock of the serial data rate. The sampling
clock is used by the transmitter for data bit shifting and receiver for data sampling.
The BRG divisor (DLL, DLM and DLD registers) defaults to 1 (DLL = 0x01, DLM = 0x00, DLD = 0x00). The
DLL and DLM registers provide the integer part of the divisor and the DLD register provides the fractional part
of the divisor. Only the four lower bits of the DLD are implemented and they are used to select a value from 0
(for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator Registers DLL,
DLM and DLD provides the capability for selecting the operating data rate. Table 11 shows the divisor for some
standard and non-standard data rates when using the internal 125MHz clock at 16X clock rate. Table 12
shows the divisor for some standard and non-standard data rates when using the internal 62.5MHz clock at
16X clock rate. If the pre-scaler is used (MCR bit [7] = 1), the output data rate will be 4 times less than that
shown in Table 11 and Table 12. At 8X sampling rate, these data rates would double. At 4X sampling rate,
these data rates would quadruple. Also, when using 8X or 4X sampling mode, note that the bit-time will have a
jitter (+/- 1/16) whenever the DLD is an odd number. For data rates not listed in Table 11, the divisor value can
be calculated with the following equation(s):
Required Divisor (decimal) = (125MHz or 62.5MHz clock frequency / prescaler) / (serial data rate x 16),
WITH
8XMODE =0 AND 4XMODE = 0
Required Divisor (decimal) = (125MHz or 62.5MHz clock frequency / prescaler / (serial data rate x 8),
WITH
8XMODE = 1 AND 4XMODE = 0
Required Divisor (decimal) = (125MHz or 62.5MHz clock frequency / prescaler / (serial data rate x 4),
WITH
8XMODE = 0 AND 4XMODE = 1
ROUND( (Required Divisor - TRUNC (Required Divisor) )*16)/16 + TRUNC (Required Divisor), where
DLM = TRUNC( Required Divisor) >> 8
DLL = TRUNC (Required Divisor) & 0xFF
DLD = ROUND ( (Required Divisor-TRUNC(Required Divisor) )*16)
The closest divisor that is obtainable in the V354 can be calculated using the following formula:
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
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