REV. 1.0.3 HIGH PERFORMANCE QUAD PCI-EXPRESS UART 3.7.2 Receiver Operation with FIFO FIGURE" />
參數(shù)資料
型號： XR17V354IB176-F
廠商： Exar Corporation
文件頁數(shù)： 40/66頁
文件大?。?/td> 0K
描述： IC UART PCIE 256B QUAD 176FPBGA
產(chǎn)品培訓(xùn)模塊： PCIe UARTs
標準包裝： 160
特點： *
通道數(shù)： 4，QUART
FIFO's： 256 字節(jié)
規(guī)程： RS485
電源電壓： 3.3V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 176-LFBGA
供應(yīng)商設(shè)備封裝： 176-FPBGA（13x13）
包裝： 托盤
其它名稱： 1016-1472
XR17V354IB176-F-ND
XR17V354
45
REV. 1.0.3
HIGH PERFORMANCE QUAD PCI-EXPRESS UART
3.7.2
Receiver Operation with FIFO
FIGURE 16. RECEIVER OPERATION IN FIFO AND FLOW CONTROL MODE
Receive Data Shift
Register (RSR)
16X or 8X or 4X
Clock
Er
ro
rFl
ag
s
(2
56-s
ets)
Er
ro
rFl
ag
si
n
LS
R
b
its
4:2
256 bytes by
11-bits wide FIFO
Receive Data Characters
FIFO Trigger=128
Example:
- FIFO trigger level set at 128 bytes
- RTS/DTR hyasteresis set at +/-32 chars.
Data fills to 160
Data falls to 96
Data Bit
Validation
Receive Data
FIFO
(256-byte)
Receive
Data
Receive Data
Byte and Errors
RHR Interrupt (ISR bit-2) is programmed
at FIFO trigger level (RXTRG).
FIFO is Enable by FCR bit-0=1
RTS#/DTR# de-asserts when data fills above
the trigger level to suspend remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
RTS#/DTR# re-asserts when data falls below
the trigger level to restart remote transmitter.
Enable by EFR bit-6=1, MCR bit-2.
3.7.3
Normal Multidrop (9-bit) Mode
Normal multidrop mode is enabled when DLD[6] = 1 and EFR[5] = 0 (Special Character Detect disabled). The
receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes.
With the receiver initially disabled (MSR[2] = 1), it ignores all the data bytes (parity bit = 0) until an address byte
is received (parity bit = 1). This address byte will cause the UART to set the parity error. The UART will
generate an LSR interrupt and place the address byte in the RX FIFO. The software then examines the byte
and enables the receiver if the address matches its slave address, otherwise, it does not enable the receiver.
If the receiver has been enabled, the receiver will receive the subsequent data. If an address byte is received,
it will generate an LSR interrupt. The software again examines the byte and if the address matches its slave
address, it does not have to do anything. If the address does not match its slave address, then the receiver
should be disabled.
3.7.4
Auto Address Detection Mode
Auto address detection mode is enabled when DLD[6] = 1 and EFR bit-5 = 1 (Special Character Detect
enabled). The receiver is set to Force Parity 0 (LCR[5:3] = ’111’) in order to detect address bytes. The desired
slave address will need to be written into the XOFF2 register. The receiver will monitor all incoming address
bytes and compare with the programmed character in the XOFF2 register. If the received byte is a data byte or
an address byte that does not match the programmed character in the XOFF2 register, the receiver will discard
the data. Upon receiving an address byte that matches the XOFF2 character, the receiver will be automatically
enabled if not already enabled, and the address character is pushed into the RX FIFO along with the parity bit
(in place of the parity error bit). The receiver also generates an LSR interrupt. The receiver will then receive
the subsequent data. If another address byte is received and this address does not match the programmed
XOFF2 character, then the receiver will automatically be disabled and all subsequent data is ignored until there
is another address byte match with XOFF2.
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