參數(shù)資料
型號： XR17C158CV
英文描述： UART
中文描述： 異步
文件頁數(shù)： 54/55頁
文件大小： 734K
代理商： XR17C158CV
á
XR17C158
PCI BUS OCTAL UART
REV. 1.1.3
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
A
PPLICATIONS
........................................................................................................................................... 1
F
EATURES
................................................................................................................................................ 1
Figure 1. Block Diagram ......................................................................................................................... 1
Figure 2. Pin Out of the Device .............................................................................................................. 2
ORDERING
INFORMATION
........................................................................................................................... 2
PIN DESCRIPTIONS ....................................................................................................... 3
FUNCTIONAL DESCRIPTION ......................................................................................... 7
PCI Local Bus Interface ........................................................................................................ 7
1.0 XR17C158 REGISTERS ......................................................................................................................... 7
Figure 3. The XR17C158 Register Sets ................................................................................................. 8
1.1 PCI LOCAL BUS CONFIGURATION SPACE REGISTERS ............................................................................... 8
T
ABLE
1: PCI L
OCAL
B
US
C
ONFIGURATION
S
PACE
R
EGISTERS
................................................................. 8
1.2 D
EVICE
C
ONFIGURATION
R
EGISTER
S
ET
................................................................................................................ 9
T
ABLE
2: XR17C158 D
EVICE
C
ONFIGURATION
R
EGISTERS
..................................................................... 10
T
ABLE
3: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
BYTE
ALIGNMENT
........................................... 12
T
ABLE
4: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
DWORD
ALIGNMENT
....................................... 12
1.2.1 The Interrupt Status Register .................................................................................................................. 12
Figure 4. The Global Interrupt Register, INT0, INT1, INT2 and INT3 .................................................. 13
T
ABLE
5: UART C
HANNEL
[7:0] I
NTERRUPT
S
OURCE
E
NCODING
............................................................. 14
T
ABLE
6: UART C
HANNEL
[7:0] I
NTERRUPT
C
LEARING
: ........................................................................... 14
1.2.2 General Purpose 16-bit Timer/Counter. [TIMERMSB, TIMELSB, TIMER, TIMECNTL] (default 0xXX-XX-00-
00) 14
Figure 5. Timer/Counter circuit. ............................................................................................................ 14
T
ABLE
7: TIMER CONTROL R
EGISTERS
............................................................................................... 15
1.2.3 8XMODE [7:0] (default 0x00) .................................................................................................................. 15
1.2.4 REGA [15:8] is reserved (default 0x00) .................................................................................................. 15
1.2.5 RESET [23:16] (default 0x00) ................................................................................................................. 15
1.2.6 SLEEP [31:24]................................................................................................................... (default 0x00) 16
1.2.7 Device Identification and Revision .......................................................................................................... 16
1.2.9 Multi-Purpose Inputs and Outputs ........................................................................................................... 16
1.2.10 MPIO REGISTER .................................................................................................................................. 16
1.2.8 REGB Register ........................................................................................................................................ 16
Figure 6. Multipurpose input/output internal circuit .............................................................................. 17
2.0 CRYSTAL OSCILLATOR / BUFFER .................................................................................................... 18
3.0 TRANSMIT AND RECEIVE DATA ....................................................................................................... 18
3.1 FIFO DATA LOADING AND UNLOADING THROUGH THE DEVICE CONFIGURATION REGISTERS IN 32-BIT
FORMAT. 18
Figure 7. Typical oscillator connections ............................................................................................... 18
3.2 FIFO DATA LOADING AND UNLOADING THROUGH THE UART CHANNEL REGISTERS, THR AND RHR IN 8-
BIT FORMAT. 20
T
ABLE
8: T
RANSMIT
AND
R
ECEIVE
D
ATA
R
EGISTER
IN
B
YTE
FORMAT
, 16C550
COMPATIBLE
..................... 20
4.0 UART ..................................................................................................................................................... 20
4.1 P
ROGRAMMABLE
B
AUD
R
ATE
G
ENERATOR
........................................................................................................... 20
Figure 8. Baud Rate Generator ............................................................................................................ 21
T
ABLE
9: T
YPICAL
DATA
RATES
WITH
A
14.7456 MH
Z
CRYSTAL
OR
EXTERNAL
CLOCK
AT
16X S
AMPLING
.. 21
4.2 A
UTOMATIC
H
ARDWARE
(RTS/CTS
OR
DTR/DSR) F
LOW
C
ONTROL
O
PERATION
.................................................. 22
Figure 9. Auto RTS/DTR and CTS/DSR Flow Control Operation ........................................................ 23
4.3 I
NFRARED
M
ODE
................................................................................................................................................. 23
Figure 10. Infrared Transmit Data Encoding and Receive Data Decoding .......................................... 24
4.4 I
NTERNAL
L
OOPBACK
........................................................................................................................................... 24
Figure 11. Internal Loop Back .............................................................................................................. 25
4.5 UART CHANNEL CONFIGURATION REGISTERS AND ADDRESS DECODING. ......................................... 25
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