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PCI BUS OCTAL UART
XR17C158
REV. 1.1.3
18
MPIOINV [7:0] (default 0x00)
Input inversion control. A logic 0 (default) does not in-
vert the input pin logic. A logic 1 inverts the input logic
level.
MPIOSEL [7:0] (default 0xFF)
Multipurpose input/output pin select. This register de-
fines the functions of the pins. A logic 1 (default) de-
fines the pin for input and a logic "0" for output.
2.0
The 158 includes an on-chip oscillator (XTAL1 and
XTAL2). The crystal oscillator provides the system
clock to the Baud Rate Generators (BRG) in each of
the 8 UARTs, the 16-bit general purpose timer/
counter and internal logics. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin
being the output. See Programmable Baud Rate
Generator in the UART section for programming de-
tails.
The on-chip oscillator is designed to use an industry
standard microprocessor crystal (parallel resonant
with 10-22 pF capacitance load, 100ppm) connected
externally between the XTAL1 and XTAL2 pins (see
Figure 7
). Alternatively, an external clock can be con-
nected to the XTAL1 pin to clock the internal 8 baud
rate generators for standard or custom rates. Typical-
ly, the oscillator connections are shown in Figure 7.
For further reading on oscillator circuit please see ap-
plication note DAN108 on EXAR’s web site.
CRYSTAL OSCILLATOR / BUFFER
3.0
There are two methods to load transmit data and un-
load receive data from each UART channel. First,
there is a transmit data register and receive data reg-
ister for each UART channel in the device configura-
tion register set to ease programming. These regis-
ters support 8, 16
,
24 and 32 bits wide format. In the
32-bit format, it increases the data transfer rate on the
PCI bus. Additionally, a special register location pro-
vides receive data byte with its associated error flags.
This is a 16-bit or 32-bit read operation where the
Line Status Register (LSR) content in the UART
channel register is paired along with the data byte.
This operation further facilitates data unloading with
the error flags without having to read the LSR register
separately. Furthermore, the XR17C158 supports
PCI burst mode for read/write operation of up to 64
bytes of data.
The second method is through each UART channel’s
transmit holding register (THR) and receive holding
register (RHR). The THR and RHR registers are
16550 compatible so their access is limited to 8-bit
format. The software driver must separately read the
LSR content for the associated error flags before
reading the data byte.
3.1
FIFO
DATA LOADING AND UNLOADING
THROUGH THE DEVICE CONFIGURATION
REGISTERS IN 32-BIT FORMAT.
The transmit and receive data registers are defined
for channel 0 to channel 7 with each channel having
it’s own address as shown in
Table 2
for faster loading
and unloading. The following paragraphs illustrate the
receive and transmit data registers in more detail.
Each Channel Normal Receive Data FIFO
Address
for channels 0 to 7 are at 0x0100, 0x0300, 0x0500,
0x0700, 0x0900, 0x0B000, 0x0D00 and 0x0F00.
TRANSMIT AND RECEIVE DATA
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIO3T Register
Multipurpose Output 3-state Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOINV Register
Multipurpose Input Signal Inversion Enable
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
MPIO6
MPIO7
MPIO5 MPIO4 MPIO3 MPIO2 MPIO1 MPIO0
MPIOSEL Register
Multipurpose Input/Output Selection
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
F
IGURE
7. T
YPICAL
OSCILLATOR
CONNECTIONS
C1
22-47pF
C2
22-47pF
14.7456
MHz
XTAL1
XTAL2
R=300K to 400K