參數資料
型號: XR17C158CV
英文描述: UART
中文描述: 異步
文件頁數: 12/55頁
文件大小: 734K
代理商: XR17C158CV
á
PCI BUS OCTAL UART
XR17C158
REV. 1.1.3
12
1.2.1
The XR17C158 has a 32-bit wide register [INT0,
INT1, INT2 and INT3] to provide interrupt information
and supports two interrupt schemes. The first
scheme is an 8-bitan 8-bit indicator representing all 8
channels with each bit representing each channel
from 0 to 7. This permits the interrupt routine to quick-
The Interrupt Status Register
ly vector and serve that UART channel and determine
the source(s) in each individual routines. INT0 bit-0
represents the interrupt status for UART channel 0
when its transmitter, receiver, line status, or modem
port status requires service. Other bits in the INT0
register provide indication for the other channels with
bit-7 representing UART channel 7 respectively.
T
ABLE
3: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
BYTE
ALIGNMENT
A
DDRESS
[A7:A0]
R
EGISTER
R
EAD
/W
RITE
C
OMMENT
RESET
STATE
Ox080
Ox081
Ox082
Ox083
INT0 [7:0]
INT1 [15:8]
INT2 [23:16]
INT3 [31:24]
Read-only Interrupt [7:0]
Read-only
Read-only
Read-only
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Ox084
Ox085
Ox086
Ox087
TIMERCNTL
TIMER
TIMERLSB
TIMERMSB
Read/Write Timer Control
Reserved
Read/Write Timer LSB
Read/Write Timer MSB
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Ox088
Ox089
Ox08A
Ox08B0
8XMODE
REGA
RESET
SLEEP
Read/Write
Reserved
Write-only Self clear bits after executing Reset
Read/Write Sleep mode
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Ox08C
Ox08D
Ox08E
Ox08F
DREV
DVID
REGB
MPIOINT
Read-only Device revision
Read-only Device identification
Write-only
Read/Write MPIO interrupt mask
Bits 7-0 = 0x02
Bits 7-0 = 0x28
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Ox090
Ox091
Ox092
Ox093
MPIOLVL
MPIO3T
MPIOINV
MPIOSEL
Read/Write MPIO level control
Read/Write MPIO output control
Read/Write MPIO input polarity select
Read/Write MPIO select
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0xFF
T
ABLE
4: D
EVICE
C
ONFIGURATION
R
EGISTERS
SHOWN
IN
DWORD
ALIGNMENT
A
DDRESS
R
EGISTER
B
YTE
3 [31:24]
B
YTE
2 [23:16]
B
YTE
1 [15:8]
B
YTE
0 [7:0]
0x080
-
083
INTERRUPT (read-only)
INT3
INT2[
INT1
INT0
0x084-087
0x088-08B
0x08C-08F
0x090-093
TIMER (read/write)
ANCILLARY1 (read/write)
ANCILLARY2 (read-only)
MPIO (read/write)
TIMERMSB
SLEEP
MPIOINT
MPIOSEL
TIMERLSB
RESET
REGB
MPIOINV
TIMER (reserved)
REGA (reserved)
DVID
MPIO3T
TIMERCNTL
8XMODE
DREV
MPIOLVL
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