參數(shù)資料
型號(hào): XR17C158CV
英文描述: UART
中文描述: 異步
文件頁(yè)數(shù): 40/55頁(yè)
文件大?。?/td> 734K
代理商: XR17C158CV
á
PCI BUS OCTAL UART
XR17C158
REV. 1.1.3
40
TFCNT[7:0]: Transmit FIFO Level Counter, read-
only
Transmit FIFO level byte count from 0x00 (zero) to
0x40 (64). This 8-bit register gives an indication of the
number of characters in the transmit FIFO. The FIFO
level Byte count register is read only. The user can
take advantage of the FIFO level byte counter for fast-
er data loading to the transmit FIFO, which reduces
CPU bandwidth requirements.
TXTRG [7:0]: Transmit FIFO Trigger Level, write
only.
An 8-bit value written to this register sets the TX FIFO
trigger level from 0x00 (zero) to 0x40 (64). The TX
FIFO trigger level generates an interrupt whenever
the data level in the transmit FIFO falls below this pre-
set trigger level.
RFCNT[7:0]: Receive FIFO Level Counter, read
only
Receive FIFO level byte count from 0x00 (zero) to
0x40 (64). It gives an indication of the number of
characters in the receive FIFO. The FIFO level byte
count register is read only. The user can take advan-
tage of the FIFO level byte counter for faster data un-
loading from the receiver FIFO, which reduces CPU
bandwidth requirements.
RXTRG[7:0]: Receive FIFO Trigger Level, write
only
An 8-bit value written to this register, sets the RX
FIFO trigger level from 0x00 (zero) to 0x40 (64). The
RX FIFO trigger level generates an interrupt whenev-
er the receive FIFO level rises to this preset trigger
level.
T
ABLE
19: UART RESET CONDITIONS
REGISTERS
RESET STATE
DLL
DLM
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
Bits 3-0 = logic 0
Bits 7-4 = logic levels of the inputs
Bits 7-0 = 0xFF
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x00
SPR
FCTR
EFR
TFCNT
TFTRG
RFCNT
RFTRG
XCHAR
XON1
XON2
XOFF1
XOFF2
I/O SIGNALS
RESET STATE
TX[ch-7:0]
IRTX[ch-7:0]
RTS#[ch-7:0]
DTR#[ch-7:0]
EECK
EECS
EEDI
Logic 1
Logic 0
Logic 1
Logic 1
Logic 0
Logic 0
Logic 0
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