參數(shù)資料
型號: XR17C158CV
英文描述: UART
中文描述: 異步
文件頁數(shù): 13/55頁
文件大?。?/td> 734K
代理商: XR17C158CV
XR17C158
PCI BUS OCTAL UART
á
REV. 1.1.3
13
The second scheme provides detail about the source
of the interrupts for each UART channel. All the inter-
rupts are encoded into a 3-bit code. This 3-bit code
represents 7 interrupts corresponding to individual
UART’s transmitter, receiver, line status, modem port
status. INT1, INT2 and INT3 registers provide the 24-
bit interrupt status for all 8 channels. Bits 8,9 and 10
representing channel 0 and bits 29, 30 and 31 repre-
senting channel 7 respectively. All 8 channel inter-
rupts status are available with a single DWORD read
operation. This feature allows the
host quickly vectors
and serves the interrupts, reducing service interval,
hence, reduce host bandwidth requirement.
All bits start up zero. A special interrupt condition is
generated by the 158 upon awakening from sleep af-
ter all 8 channels were put to sleep mode earlier.
Figure 4
shows the 4-byte interrupt register and its
make up.
INT0 [7:0] Channel Interrupt Indicator.
Each bit gives an indication of the channel that has
requested for service. Bit-0 represents channel 0 and
bit-7 indicates channel 7. Logic one indicates the
channel N [7:0] has called for service. The interrupt
bit clears after reading the appropriate register of the
interrupting channel register, see Interrupt Clearing
section.
INT3, INT2 and INT1 [32:8] Twenty four bit encoded
interrupt indicator. Each channel’s interrupt is encod-
ed into 3 bits for receive, transmit, and status. Bit
[10:8] represent channel 0 and go up to channel 7
with bits [31:29]. The 3 bit encoding and their priority
order are shown below in Table 5. The Timer and
MPIO interrupts are for the device and therefore they
exist within channel 0 space and not in other channel
interrupt.
.
GLOBAL INTERRUPT REGISTER (DWORD) [de-
fault 0x00-00-00-00]
INT3 [31:24]
INT2 [23:16]
INT1 [15:87]
INT0 [7:0]
The INT0 register provides individual status for
each channel
INT0 Register
Individual UART Channel Interrupt Status
Ch-6
Ch-7
Ch-5 Ch-4 Ch-3 Ch-2 Ch-1 Ch-0
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
F
IGURE
4. T
HE
G
LOBAL
I
NTERRUPT
R
EGISTER
, INT0, INT1, INT2
AND
INT3
Channel-3
Channel-2
Channel-1
Channel-0
INT2 Register
INT1 Register
INT3 Register
INT0 Register
Rsvd
Interrupt Registers,
INT0, INT1, INT2 and INT3
Bit-0
Bit-1
Bit-2
Bit-3
Bit-7
Bit-4
Bit-5
Bit-6
Ch-3
Ch-2
Ch-1
Ch-0
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Bit
N+1
Bit
N+2
Bit
N
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
Rsvd
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