參數(shù)資料
型號： XC3S200AN-4FT256I
廠商： Xilinx Inc
文件頁數(shù)： 79/123頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 3AN 256FTBGA
標(biāo)準(zhǔn)包裝： 90
系列： Spartan®-3AN
LAB/CLB數(shù)： 448
邏輯元件/單元數(shù)： 4032
RAM 位總計： 294912
輸入/輸出數(shù)： 195
門數(shù)： 200000
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 256-LBGA
供應(yīng)商設(shè)備封裝： 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
59
Suspend Mode Timing
X-Ref Target - Figure 12
Figure 12: Suspend Mode Timing
Table 49: Suspend Mode Timing Parameters
Symbol
Description
Min
Typ
Max
Units
Entering Suspend Mode
TSUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter
(suspend_filter:No)
–7
–ns
TSUSPENDFILTER
Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled
(suspend_filter:Yes)
+160
+300
+600
ns
TSUSPEND_GTS
Rising edge of SUSPEND pin until FPGA output pins drive their defined
SUSPEND constraint behavior
–10
–ns
TSUSPEND_GWE
Rising edge of SUSPEND pin to write-protect lock on all writable clocked
elements
–< 5
–ns
TSUSPEND_DISABLE
Rising edge of the SUSPEND pin to FPGA input pins and interconnect
disabled
–
340
–ns
Exiting Suspend Mode
TSUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin
Does not include DCM lock time
–
4 to 108
–s
TSUSPEND_ENABLE
Falling edge of the SUSPEND pin to FPGA input pins and interconnect
re-enabled
–
3.7 to 109
–s
TAWAKE_GWE1
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1
–67
–ns
TAWAKE_GWE512
Rising edge of the AWAKE pin until write-protect lock released on all writable
clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512
–14
–s
TAWAKE_GTS1
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1
–57
–ns
TAWAKE_GTS512
Rising edge of the AWAKE pin until outputs return to the behavior described
in the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512
–14
–s
Notes:
1.
These parameters based on characterization.
2.
For information on using the Spartan-3AN Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.
DS610-3_08_061207
Blocked
t
SUSPEND_DISABLE
t
SUSPEND_GWE
t
SUSPENDHIGH_AWAKE
t
AWAKE_GWE
t
AWAKE_GTS
t
SUSPEND_GTS
SUSPEND Input
AWAKE Output
Flip-Flops, Block RAM,
Distributed RAM
FPGA Outputs
FPGA Inputs,
Interconnect
Write Protected
Defined by SUSPEND constraint
Entering Suspend Mode
Exiting Suspend Mode
sw_gts_cycle
sw_gwe_cycle
t
SUSPEND_ENABLE
t
SUSPENDLOW_AWAKE
相關(guān)PDF資料
PDF描述
XC3S400AN-4FTG256C IC FPGA SPARTAN-3AN 256FTBGA
RSA50DTAD-S664 CONN EDGECARD 100PS R/A .125 SLD
24LC32AFT-E/OT IC SRL EEPROM 4KX8 2.5V SOT23-5
RMA50DTAD-S664 CONN EDGECARD 100PS R/A .125 SLD
24AA32AFT-I/MS IC SRL EEPROM 4KX8 1.8V 8-MSOP
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC3S200AN-4FTG256C 功能描述:IC SPARTAN-3AN FPGA 200K 256FTBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S200AN4FTG256CES 制造商:Xilinx 功能描述:
XC3S200AN-4FTG256CES 制造商:Xilinx 功能描述:
XC3S200AN-4FTG256I 功能描述:IC SPARTAN-3AN FPGA 200K 256FTBG RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan®-3AN 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計:221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241
XC3S200AN-5FT256C 制造商:Xilinx 功能描述:FPGA SPARTAN-3AN 200K GATES 4032 CELLS 770MHZ 1.2V 256FTBGA - Trays 制造商:Xilinx 功能描述:IC FPGA SPARTAN-3AN 200K 256BGA 制造商:Xilinx 功能描述:IC FPGA 195 I/O 256FTBGA
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*