參數(shù)資料
型號: XC3S200AN-4FT256I
廠商: Xilinx Inc
文件頁數(shù): 55/123頁
文件大?。?/td> 0K
描述: IC FPGA SPARTAN 3AN 256FTBGA
標(biāo)準(zhǔn)包裝: 90
系列: Spartan®-3AN
LAB/CLB數(shù): 448
邏輯元件/單元數(shù): 4032
RAM 位總計(jì): 294912
輸入/輸出數(shù): 195
門數(shù): 200000
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-FTBGA
Spartan-3AN FPGA Family: DC and Switching Characteristics
DS557 (v4.1) April 1, 2011
Product Specification
37
Three-State Output Propagation Times
Table 28: Timing for the IOB Three-State Path
Symbol
Description
Conditions
Device
Speed Grade
Units
-5
-4
Max
Synchronous Output Enable/Disable Times
TIOCKHZ
Time from the active transition at the OTCLK
input of the Three-state Flip-Flop (TFF) to when
the Output pin enters the high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
0.63
0.76
ns
TIOCKON(2)
Time from the active transition at TFF’s OTCLK
input to when the Output pin drives valid data
All
2.80
3.06
ns
Asynchronous Output Enable/Disable Times
TGTS
Time from asserting the Global Three State
(GTS) input on the STARTUP_SPARTAN3A
primitive to when the Output pin enters the
high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
9.47
10.36
ns
Set/Reset Times
TIOSRHZ
Time from asserting TFF’s SR input to when the
Output pin enters a high-impedance state
LVCMOS25, 12 mA
output drive, Fast slew
rate
All
1.61
1.86
ns
TIOSRON(2)
Time from asserting TFF’s SR input at TFF to
when the Output pin drives valid data
All
3.57
3.82
ns
Notes:
1.
The numbers in this table are tested using the methodology presented in Table 30 and are based on the operating conditions set forth in
2.
This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 29.
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