參數(shù)資料
型號(hào)： WEDPNF8M722V-1015BI
廠商： WHITE ELECTRONIC DESIGNS CORP
元件分類： 存儲(chǔ)器
英文描述： SPECIALTY MEMORY CIRCUIT, PBGA275
封裝： 32 X 25 MM, PLASTIC, BGA-275
文件頁(yè)數(shù)： 8/43頁(yè)
文件大?。?/td> 1280K
代理商： WEDPNF8M722V-1015BI
16
White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M722V-XBX
TABLE 4 - DEVICE BUS OPERATIONS
LEGEND:
L
= Logic Low = VIL
X
= Don’t Care
FDOUT = Flash Data Out
H
= Logic High = VIH
FAIN= Flash Address In
VID = 12.0 ± 0.5V
FDIN = Flash Data In
NOTES:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector Protection/Unprotection" section.
2. Addresses are FA18: FA0 in word mode (BYTE1-2 = VIH), FA18: FA-1 in byte mode (BYTE1-2 = VIL)
To writes a command or command sequence (which in-
cludes programming data to the device and erasing sec-
tors of memory), the system must drive FWE and FCS
1-2 to
VIL, and FOE to VIH.
For program operations, the BYTE1-2 pins determine
whether the device accepts program data in bytes or words.
Refer to “Word/ Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate
WRITE COMMANDS/COMMAND
SEQUENCES
that no spurious alteration of the memory content occurs
during the power transition. No command is necessary in
this mode to obtain array data. Standard microprocessor
read cycles that asser t valid addresses on the device data
outputs. The device remains en-abled for read access until
the command register contents are altered.
See “Reading Array Data” for more information. Refer to the
Flash AC Read-only Operations table for timing specifica-
tions and to Figure 11 for the timing diagram. IFCC1 in the
ICC Specifications and Conditions table represents the ac-
tive current specification for reading array data.
faster programming. Once the device enters the Unlock By-
pass mode, only two write cycles are required to program
a byte, instead of four.
An erase operation can erase one sector, multiple sectors,
or the entire device. Table 5 indicates the address space
that each sector occupies. A “sector address” consists of
the address bits required to uniquely select a sector. The
“Flash Command Defini-tions” section has details on eras-
ing a sector or the entire chip, or suspending/resuming the
erase operation.
After the system writes the autoselect command sequence,
the device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on FD
7-0 and FD23-16 re-
spectively . Stan-dard read cycle timings apply in this mode.
Refer to the “Autoselect Mode” and “Autoselect Command
Sequence” sections for more information.
IFCC2 in the DC Characteristics table represents the active
current specifications for the write mode. The “Flash AC
Characteristics” section contains timing specification tables
and timing diagrams for write operations.
FD
8-15
8-15/FD
/FD
24-31
Operation
FC
FCS
S
1-2
FOE
FWE
RST
Addresses (2)
FD
0-7
0-7/FD1
/FD1
6-23
BYTE1-2
=VIH
=VIL
Read
L
H
FAIN
FDOUT
FD8-14, 24-30 = High Z
Write
L
H
L
H
FAIN
FDOUT
FD15, 31 = FA-1
Standby
VCC± 0.3V
X
VCC ± 0.3V
X
High Z
Output Disable
L
H
X
High Z
Reset
X
L
X
High Z
Sector Address
Sector Protect (1)
L
H
L
VID
FA6 = L, FA1 = H,
FDIN
X
FA0 = L
Sector Address
Sector Unprotect (1)
L
H
L
VID
FA6 = L, FA1 = H,
FDIN
X
FA0 = L
Temporary Sector Unprotect
X
VID
AIN
FDIN
High Z
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