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參數(shù)資料
| 型號(hào)： | WEDPNF8M722V-1015BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 16/43頁 |
| 文件大小： | 1280K |
| 代理商： | WEDPNF8M722V-1015BI |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
White Electronic Designs
WEDPNF8M722V-XBX
ERASE OPERATION
1. See Table 5 for erase command sequence.
2. See "FD3 : Sector Erase Timer" for more information.
FIG. 7
SECTOR ERASE COMMAND
SEQUENCE
Sector erase is six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock
cycles, followed by a setup command. Two additional un-
lock write cycles are then followed by the address of the
sector to be erased, and the sector erase command, which
in turn invokes the Embedded Erase algorithm. Table 7
shows the address and data requirements for the sector
erase command sequence.
The device does
not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm au-
tomatically programs and verifies the entire memory for an
all zero data pattern prior to electrical erase. The system is
not required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
Chip erase is six bus cycle operation. The chip erase com-
mand sequence is initiated by writing two unlock cycles,
followed by a setup command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does
not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically programs and
verifies the entire memory for an all zero data pattern prior
to electrical erase. The system is not required to provide
any controls or timings during these operations. Table 7
shows the address and data requirements for the chip erase
command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. Note that a hardware reset
hardware reset
during the chip erase operation immediately terminates the
operation. The Chip Erase command sequence should be
re-initiated once the device has returned to reading array
data, to ensure data integrity.
The system can determine the status of the erase operation
by using FD7, FD6, or FD2, or RY/BY1 and FD23, FD22, FD18
or RY/BY2, respectively. See “Write Operation Status” for in-
formation on these status bits. When the Embedded Erase
algorithm is complete, the device returns to reading array
data and addresses are no longer latched.
Figure 6 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in “Flash AC Character-
istics” for parameters, and to Figure 12 for timings diagram.
CHIP ERASE COMMAND SEQUENCE
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參數(shù)描述 |
|---|---|
| WEDPNF8M722V-1015BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1212BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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