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參數(shù)資料
| 型號(hào)： | WEDPNF8M722V-1015BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲(chǔ)器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 13/43頁 |
| 文件大?。?/td> | 1280K |
| 代理商： | WEDPNF8M722V-1015BI |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M722V-XBX
FLASH COMMAND DEFINITIONS
READ ARRAY DATA
Upon initial device power-up the device defaults to read
array data. No commands are required to retrieve data. The
device is also ready to read array data after it has completed
an Embedded Program or Embedded Erase algorithm.
After the device accepts an Erase Suspend command, the
device enters the Erase Suspend mode. The system can
read array data using the standard read timings, except that
if it reads at an address within erase-suspend sectors, the
device outputs status data. After completing a program-
ming operation in the Erase Suspend mode, the system may
once again read array data with the same exception. See
“Erase Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system
must issue the reset command to re-enable the
device for reading array data if FD5 goes high, or while in the
autoselect mode. See the “Reset Command” section, next.
See also “Requirements for Reading Array Data” on the “Bus
Operations” section for more information. The Data Sheet
Read Operations table provides the read parameters, and the
Read Operations Timing Diagram shows the timing diagram.
Writing specific address and data commands or sequences
into the command register initiates device operations. Table
7 defines the valid register command sequences. W
W
Writing
riting
incor
incorrect address and data values or writing them in
rect address and data values or writing them in
improper sequence will reset the device to the read
ar
ar ray data
ray data
ray data.
All addresses are latched on falling edge of FWE or FCS1-2,
whichever occurs later. All data is latched on the rising edge
of FWE or FCS1-2, whichever occurs first. Refer to the ap-
propriate timing diagrams in the “Flash AC Characteristics”
section.
RESET COMMAND
Writing the reset command to the device resets the device
to reading array data. Address bits are “don't care” for this
command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing be-
gins. This resets the device to reading array data. Once era-
sure begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the sequence
cycles in a program command sequence before program-
ming begins. This resets the device to reading array data
(also applies to programming in Erase Suspend mode).
Once programming begins, however, the device ignores
reset commands until the operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in
autoselect mode, the reset command
must be written to
return to reading array data (also applies to autoselect dur-
ing Erase Suspend mode).
If FD5 or FD21, respectively goes high during a program or
erase operation, writing the reset command returns the de-
vice to reading array data (also applies during Erase Suspend).
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 5ns (typical) on FOE, FCS1-2 or
FWE do not initiate a write cycle.
LOGICAL INHIBIT
Write cycles are inhibited by holding any one of FOE = VIL,
FCS1-2 = VIH or FWE = VIH. To initiate a write cycle, FCS1-2
and FWE must be a logical zero while FOE is a logical one.
POWER-UP WRITE INHIBIT
If FWE = FCS1-2 = VIL and FOE = VIH during power up,
the device does not accept commands on the rising edge
of FWE. The internal state machine is automatically reset to
reading array data on power-up.
SECTOR PROTECTION/
UNPROTECTION
The hardware sector protection feature disables both pro-
gram and erase operations in any sector. The hardware sec-
tor unprotection feature re-enables both program and erase
operations in previ-ously protected sectors.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
This operation requires VID on the RST pin only, and can be
implemented either in-system or via programming equip-
ment. The timing diagram is shown in figure 18. This method
uses standard microprocessor bus cycle timing. For sector
unprotect, all unpro-tected sectors must first be protected
prior to the first sector unprotect write cycle.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M722V-1015BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1212BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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