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參數(shù)資料
| 型號： | WEDPNF8M722V-1015BI |
| 廠商： | WHITE ELECTRONIC DESIGNS CORP |
| 元件分類： | 存儲器 |
| 英文描述： | SPECIALTY MEMORY CIRCUIT, PBGA275 |
| 封裝： | 32 X 25 MM, PLASTIC, BGA-275 |
| 文件頁數(shù)： | 17/43頁 |
| 文件大?。?/td> | 1280K |
| 代理商： | WEDPNF8M722V-1015BI |
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White Electronic Designs Corporation Phoenix AZ (602) 437-1520
White Electronic Designs
WEDPNF8M722V-XBX
The Erase Suspend command allows the system to inter-
rupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50s time-out period during the sector erase
command sequence. The Erase Suspend command is ig-
nored if written during the chip erase operation or Embed-
ded Program algorithm. Writing the Erase Suspend command
during the Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation. Ad-
out of 50s begins. During the time-out period, additional
sector addresses and sector erase commands may be writ-
ten. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one
sector to all sectors. The time between these additional
cycles must be less than 50s, otherwise the last address
and command might not be accepted, and erasure may
begin. It is recommended that processor interrupts can be
re-enabled after the last Sector Erase command is written.
If the time between additional sector erase commands can
out period resets the device to reading ar
out period resets the device to reading array data
ray data
ray data.
The system must rewrite the command sequence and any
additional sector addresses and commands.
The system can monitor FD3 and FD19, respectively to de-
termine if the sector erase timer has timed out. See the
“FD3/FD19: Sector Erase Timer ” section. The time-out be-
gins from the rising edge of the final FWE pulse in com-
mand sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other command is valid. All
other commands are ignored. Note that a hardware reset
during the sector erase operation. The Sector Erase com-
mand sequence should be reinitiated once the device has
returned to reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no
longer latched. The system can determine the status of
the erase operation by using FD7, FD6, or FD2, or RY/BY1
and FD23, FD22, or FD18, or RY/BY2. See “Write Operation
Status” for information on these status bits.
Figure 6 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in the “Flash AC Charac-
teristics” for parameters, and to Figure 12 for timings diagram.
ERASE SUSPEND/ERASE RESUME
COMMAND SEQUENCE
dresses are “don't cares” when writing the Erase Suspend
command.
When the Erase Suspend command is written during a sec-
tor erase operation, the device requires a maximum of 20s
to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the system
can read array data from or program data to any sector not
selected for erasure. (The device “erase suspends” all sec-
tors selected for erasure.) Normal read and write timings
and command definitions apply. Reading at any address
within erase-suspended sectors produces status data on
FD7-0 and FD23-16 respectively. The system can use FD7,
or FD6, and FD2 and FD23 or FD22 and FD18 together re-
spectively, to determine if a sector is actively erasing or is
erase suspended. See "Write Operation Status" for infor-
mation on these status bits.
After an erase-suspended program operation is complete,
the system can once again read array data within non-sus-
pended sectors. The system can determine the status of
the program operation using the FD7 or FD6 status bits and
FD23 or FD22 status bits respectively, just as in the standard
program operation. See the “Write Operation Status” for
more information.
The system may also write the autoselect command se-
quence when the device is in the Erase Suspend mode.
The device allows reading autoselect codes even at ad-
dresses within erasing sectors, since the codes are not
stored in the memory array. When the device exits the
autoselect mode, the device reverts to the Erase Suspend
mode, and is ready for another valid operation.
The system must write the Erase Resume command (address
bits are “don't care”) to exit the erase suspend mode and
continue the sector erase operation. Further writes of the
Resume command are ignored. Another Erase Suspend com-
mand can be written after the device has resumed erasing.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M722V-1015BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1210BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1212BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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