參數資料
型號: W9412G6CH-5
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁數: 8/55頁
文件大?。?/td> 2011K
代理商: W9412G6CH-5
W9412G6CH
Publication Release Date:Nov. 19, 2007
- 16 -
Revision A07
7.10.3 CAS Latency field (A6 to A4)
This field specifies the number of clock cycles from the assertion of the Read command to the first
data read. The minimum values of CAS Latency depend on the frequency of CLK.
A6
A5
A4
CAS LATENCY
0
Reserved
0
1
Reserved
0
1
0
2
0
1
3
1
0
Reserved
1
0
1
Reserved
1
0
2.5
1
Reserved
7.10.4 DLL Reset bit (A8)
This bit is used to reset DLL. When the A8 bit is “1”, DLL is reset.
7.10.5 Mode Register/Extended Mode register change bits (BS0, BS1)
These bits are used to select MRS/EMRS.
BS1
BS0
A11-A0
0
Regular MRS Cycle
0
1
Extended MRS Cycle
1
x
Reserved
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