參數(shù)資料
型號: W9412G6CH-5
廠商: WINBOND ELECTRONICS CORP
元件分類: DRAM
英文描述: 8M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝: 0.400 INCH, 0.65 MM PITCH, ROHS COMPLIANT, TSOP2-66
文件頁數(shù): 14/55頁
文件大小: 2011K
代理商: W9412G6CH-5
W9412G6CH
Publication Release Date: Nov. 19, 2007
- 21 -
Revision A07
Function Truth Table, continued
CURRENT
STATE
CS
RAS CAS
WE
ADDRESS
COMMAND
ACTION
NOTES
H
X
DSL
NOP->Row active after tWR
L
H
X
NOP
NOP->Row active after tWR
L
H
L
X
BST
ILLEGAL
L
H
L
H
BS, CA, A10
READ/READA
ILLEGAL
3
L
H
L
BS, CA, A10
WRIT/WRITA
ILLEGAL
3
L
H
BS, RA
ACT
ILLEGAL
3
L
H
L
BS, A10
PRE/PREA
ILLEGAL
3
L
H
X
AREF/SELF
ILLEGAL
Write
Recovering
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
DSL
NOP->Enter precharge after
tWR
L
H
X
NOP
NOP->Enter precharge after
tWR
L
H
L
X
BST
ILLEGAL
L
H
L
H
BS, CA, A10
READ/READA
ILLEGAL
3
L
H
L
BS, CA, A10
WRIT/WRITA
ILLEGAL
3
L
H
BS, RA
ACT
ILLEGAL
3
L
H
L
BS, A10
PRE/PREA
ILLEGAL
3
L
H
X
AREF/SELF
ILLEGAL
Write
Recovering
with Auto-
precharge
L
Op-Code
MRS/EMRS
ILLEGAL
H
X
DSL
NOP->Idle after TRC
L
H
X
NOP
NOP->Idle after TRC
L
H
L
X
BST
ILLEGAL
L
H
L
H
X
READ/WRIT
ILLEGAL
L
H
X
ACT/PRE/PREA
ILLEGAL
Refreshing
L
X
AREF/SELF/MRS/EMRS
ILLEGAL
H
X
DSL
NOP->Row after tMRD
L
H
X
NOP
NOP->Row after tMRD
L
H
L
X
BST
ILLEGAL
L
H
L
X
READ/WRIT
ILLEGAL
Mode
Register
Accessing
L
X
ACT/PRE/PREA/ARE
F/SELF/MRS/EMRS
ILLEGAL
Notes
:
1. All entries assume that CKE was active (High level) during the preceding clock cycle and the current clock cycle.
2. Illegal if any bank is not idle.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BS), depending on the
state of that bank.
4. Illegal if tRCD is not satisfied.
5. Illegal if tRAS is not satisfied.
6. Must satisfy burst interrupt condition.
7. Must avoid bus contention, bus turn around, and/or satisfy write recovery requirements.
8. Must mask preceding data which don’t satisfy tWR
Remark: H = High level, L = Low level, X = High or Low level (Don’t Care), V = Valid data
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