參數(shù)資料
型號： VSC870
廠商： VITESSE SEMICONDUCTOR CORP
元件分類： 通用總線功能
英文描述： High Performance Serial Backplane Transceiver
中文描述： LINE TRANSCEIVER, PBGA192
封裝： BGA-192
文件頁數(shù)： 3/40頁
文件大?。?/td> 511K
代理商： VSC870
VITESSE
Data Sheet
VSC870
High Performance Serial
Backplane Transceiver
G52190-0, Rev 4.1
01/05/01
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Package Pin Descriptions
Symbol
Name
I/O
Freq
Type
Description
TXIN[31:0]
Transmit Parallel Data In
I
62.5Mb/s
TTL
32-bit parallel data input for the transmit side.
TXTYP[1:0]
Transmit Word Type
I
62.5Mb/s
TTL
If BYPASS is LOW, these signals designate the transmit
word type. If BYPASS is HIGH, these signals directly
control the overhead bits sent on the serial channel.
When TXEN is HIGH, TXIN[31:0], TXTYP[1:0] are
loaded in to the transceiver on the next WCLK. When
TXEN is LOW, the transceiver ignores TXIN[31:0] and
TXTYP[1:0] and sends IDLE words at the serial output.
When RTR is HIGH, the receiving side memory system is
ready to receive data. If LOW, it sends a back pressure
(flow control) signal to the source port card telling it to
stop sending data. In Cell Mode, set RTR LOW to cell
synchronize to the external cell clock. If RTR is HIGH,
cell clock is recovered from the bit stream.
In Packet Mode, when BYPASS is LOW, RTM/TCLK is
set HIGH at the beginning of each data transmission and
set LOW when the data packet has been successfully sent
to all outputs. In Cell Mode, a HIGH pulse represents the
transmit cell clock.
When BYPASS is LOW, RFM is set HIGH whenever a
retransmission of data is required due to contention for
destination ports.
This signal is LOW if MODE[1] is HIGH and the
transceiver is word aligned on the transmit side. After
initialization it will go HIGH for one word clock if there
is a cell clock error.
When REN is HIGH, the transceiver is ready to read data
at TXIN[31:0] and TXTYP[1:0]. This signal can be
forced low by the received flow control signal.
These mode control pins are used to configure link
synchronization. See Section 1.5.
TXEN
Transmit Enable
I
62.5Mb/s
TTL
RTR
Ready To Receive
I
62.5Mb/s
TTL
RTM/TCLK
Retransmit Mode/
Transmit Cell Clock
O
62.5Mb/s
TTL
RFM
Read From Mark
O
62.5Mb/s
TTL
TXOK
Transmit signal OK
O
<1MHz
TTL
REN
Read Enable
O
62.5Mb/s
TTL
MODE[1:0]
Mode Control
I
<1MHz
TTL
2.125Gb/s
LVDS
2.125Gb/s
LVDS
<1MHz
TTL
2.125Gb/s
LVDS
2.125Gb/s
LVDS
TXSA+/
TXSA-
TXSB+/
TXSB-
Transmit Serial Output A
O
High speed serial differential transmit channel A
Transmit Serial Output B
O
High speed serial differential transmit channel B
LOOPBACK
Loop Back
I
When LOOPBACK is HIGH, the CRU and signal
detector select the serial data output channel as an input.
RXSA+/
RXSA-
RXSB+/
RXSB-
Receive Serial Input A
I
High speed serial differential receive channel A
Receive Serial Input B
I
High speed serial differential receive channel B
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