參數(shù)資料
型號(hào)： VSC870
廠(chǎng)商： VITESSE SEMICONDUCTOR CORP
元件分類(lèi)： 通用總線(xiàn)功能
英文描述： High Performance Serial Backplane Transceiver
中文描述： LINE TRANSCEIVER, PBGA192
封裝： BGA-192
文件頁(yè)數(shù)： 17/40頁(yè)
文件大小： 511K
代理商： VSC870
VITESSE
Data Sheet
VSC870
High Performance Serial
Backplane Transceiver
G52190-0, Rev 4.1
01/05/01
Page 17
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano
Camarillo, CA 93012
Tel: (800) VITESSE
FAX: (805) 987-5896
Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Camp-on with Priority means the transceiver sends a repeated sequence of connection request words to the
switch at a variable frequency until the request is granted. Multicast with Recast means the transceiver sends a fixed
number of connection request words to the switch. If some but not all outputs are granted, the packet is sent. After the
packet is transmitted successfully, the process is repeated for the rest of the ungranted outputs. In this mode, the FIFO
or memory system is required to provide retransmit capability. Multi Queue mode allows multiple unicast requests to
be sent to the switch in the same CRQ word. The switch returns data to the transceiver describing which connection
was granted. This mode also supports priority camp-on as described above. In all of these modes, to release its
connection, the port sends a new CRQ to the switch. If the CRQ does not have any output port bit set, the switch
interprets this as a connection release command. If a destination is released, the switch keeps sending IDLE words to
the destination port until a new connection is made.
2.3.1 ABORT Signal
If the CRQ cannot be granted by the switch (for example, a time out expires in the user logic), the user can set the
ABORT signal HIGH to abort the transaction. Upon detecting that the ABORT signal is HIGH, the transceiver sends
out one more CRQ command with the connection request bit map cleared. This will force the switch to release any
connections it has accumulated and all data words up to the next CRQ at the user interface will be read and ignored.
The ABORT signal has to be held HIGH longer than the round trip delay between the transceiver and switch chip (>
9 clock cycles). This guarantees that any ACK generated during that time will be discarded. If ABORT is held HIGH
for only a single cycle, then it can not be followed by another CRQ within 9 cycles. If the ABORT is set HIGH in the
middle of a packet, the transceiver will also send a CRQ to the switch to break the current connections.
2.3.2 Early Arbitration
In order to optimize throughput, early arbitration can be performed by sending the CRQ words to the switch D
words before the end of the current packet. When arbitration results are known, the arbiter reserves the switch output
for the granted input until the current data transmission is completed for that output. The end of the current
transmission is identified by the header word of the next packet. When the switch receives the header word, the
switch matrix will be reconfigured for the outputs that were reserved from the last arbitration. The maximum value
for D is based on the round-trip delay from the time the port submits a CRQ until an ACK is received and the FIFO is
ready to send a data word. In a typical system, the round trip delay is 9 cycles plus the FIFO response time. If the
transmission line delay on the serial data line is significant, this time will increase. The value of D can be set higher
than the round trip delay only if the minimum delay enable value (see section 2.3.3) is equal to the difference between
D and the round trip delay (i.e. maximum D = 9 + delay enable value). For example, if the round trip delay is 9 and D
is set to 10, the minimum delay enable value is 2. The number D is a system wide value that must be used by all port
MD[1:0]
CRQ Mode
CT[2:0] Definition
0 0
0 1
1 0
Camp-on with Priority Mode
Number of IDLE words between each CRQ word
Multicast with Recast Mode
Number of CRQ words to send in a row
Multi Queue Mode
Number of IDLE words between each CRQ word
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